Philips TDA9964 6. Block diagram

Philips Semiconductors TDA9964

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.

Objective speciﬁcation Rev. 03 — 16 January 2001 3 of 23

6. Block diagram

Fig 1. Block diagram.

FCE515

12-bit ADC

REGULATOR

CDS CLOCK GENERATOR

BLANKING OUTPUT

BUFFER

37

38

27

26

25

28

29

30

31

32

33

34

35

36

39

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

OGND2

D1

D0

23

24

VCCO1

10 DCLPC

21 VCCD1

VCCO2

22 DGND1

3

AGND2

7

VCCA2

9

CPCDS2

8

CPCDS1

4

IN

5

AGND3

11

OFDOUT

14

VCCA3

OE

43

BLK

47

CLK

40

AGND6

2

AGND1

1

VCCA1

41

VCCA4

48

CLPDM

44

CLPOB

45

SHP

SHIFT

CORRELATED

DOUBLE

SAMPLING

7-BIT

REGISTER

8-BIT

REGISTER

8-BIT

REGISTER

16

15

OPGA OPGAC

12 6 13

TEST AGND4 AGND5

46

SHD

SERIAL

INTERFACE

17

18

19

SEN SCLK SDATA

20

VSYNC

42

STDBY

PGA

CLAMP

Vref

OFD DAC

DATA

FLIP-

FLOP

CLAMP

TDA9964

OGND1

BLACK

LEVEL

SHIFT

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Contents

Main TDA9964 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Rev. 03 16 January 2001 Objective specication 1. Description 2. Features 4. Quick reference data 5. Ordering information 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Objective specication Rev. 03 16 January 2001 3 of 23 hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh 6. Block diagram Fig 1. Block diagram. TDA9964 Philips Semiconductors TDA9964 7. Pinning information Fig 2. Pin conguration. 7.2 Pin description 7.1 Pinning TDA9964HL Page Philips Semiconductors TDA9964 8. Limiting values 9. Thermal characteristics 10. Characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). = 3.0V; V = 2.7V; f = 3.0 V; V = 2.7 V; f = 30 MHz; T = 3.0 V; V = 2.7 V; f = 30 MHz; T Philips Semiconductors TDA9964 Fig 3. Pixel frequency timing diagram; all polarities active HIGH. Fig 4. Pixel frequency timing diagram; all polarities active LOW. Fig 5. DAC voltage output as a function of DAC input code. Fig 6. Line frequency timing diagram. 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Fig 7. Total gain from CDS input to ADC input as a function of PGA input code. Fig 8. Typical total noise performance as a function of PGA gain. Fig 9. Serial interface block diagram. VSYNC Fig 10. Loading sequence of control input data via the serial interface. tsu1=t Page 11. Application information D1 D0 TDA9964 Fig 11. Application diagram. 11.1 Power and grounding recommendations 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 Fig 12. SOT313-2. 13. Handling information 14. Soldering 14.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 14.2 Reow soldering 15. Revision history 16. Data sheet status 17. Denitions 18. Disclaimers Philips Semiconductors - a worldwide company Internet: http://www.semiconductors.philips.com Contents