Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 8 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
fpix(min) minimum pixel frequency tbf −−MHz
tCLKH CLK pulse width HIGH 12 −−ns
tCLKL CLK pulse width LOW 12 −−ns
td(SHD;CLK) time delay between
SHD and CLK see Figure 3 and 410 −−ns
tsu(BLK;SHD) set-uptime of BLK compared
to SHD see Figure 3 and 45−−ns
Vi(IN) video input dynamic signal
for ADC full-scale output PGA code = 00 800 −−mV
PGA code = 255 50 −−mV
Ntot(rms) total noise from CDS input to
ADC output (RMS value) seeFigure 8
PGA gain =0 dB −1.5 −LSB
PGA gain =9 dB −2.2 −LSB
Ein(rms) equivalent input noise
voltage (RMS value) PGA gain = 24 dB −70 −µV
PGA gain =9 dB −140 −µV
OCCD(max) maximum offset between
CCD floating level and CCD
dark pixel level
−100 −+100 mV
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)
Ri=1MΩ−1.0 −V
VOFDOUT(0) DCoutput voltage for code 0 −AGND −V
VOFDOUT(255) DCoutput voltage for
code 255
−AGND+ 1.0 −V
TCDAC DAC output range
temperature coefficient
−250 −ppm/°C
ZOFDOUT DAC output impedance −2000 −Ω
IOFDOUT OFD output current drive static −− 100 µA
Digital outputs (fpix =30 MHz; CL= 10 pF); see Figure 3 and 4
VOH HIGH-level output voltage IOH=−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL =1mA 0 −0.5 V
IOZ output current in 3-state
mode 0.5 V < Vo<V
CCO −20 −+20 µA
th(o) output hold time 5 −−ns
td(o) output delay time CL=10 pF; VCCO = 3.0 V −12 tbf ns
CL=10 pF; VCCO = 2.7 V −14 tbf ns
CLoutput load capacitance −− 15 pF
Serial interface
fSCLK(max) maximumfrequency of serial
interface 10 −−MHz
Table 6: Characteristics
…continued
V
CCA
=V
CCD
= 3.0 V; V
CCO
= 2.7 V; f
pix
= 30 MHz; T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit