Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 7 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
Digital inputs
Pins: SHP, SHD and CLK (referenced to DGND)
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.5 V
Iiinput current 0 ≤Vi≤5.5V −3−+3 µA
Ziinput impedance fCLK =30 MHz −50 −kΩ
Ciinput capacitance fCLK =30 MHz −− 2pF
Pins: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY,OE, BLK, VSYNC
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.5 V
Iiinput current 0 ≤Vi≤5.5V −2−+2 µA
Clamps
Global characteristics of the clamp loops
tW(clamp) clamp active pulse width in
number of pixels PGA code = 255 for
maximum 4LSB error 12 −−pixels
Input clamp (driven by CLPDM)
gm(CDS) CDS input clamp
transconductance
−20 −mS
Correlated Double Sampling(CDS)
Vi(CDS)(p-p) maximumpeak-to-peak CDS
input amplitude (video signal) VCC= 2.85 V 650 −−mV
VCC≥3.0 V 800 −−mV
Vreset(max) maximum CDS input reset
pulse amplitude 500 −−mV
Ii(IN) input current into pin IN at floating gate level tbf −tbf µA
Ciinput capacitance −2−pF
tCDS(min) CDScontrol pulses minimum
active time Vi(CDS)(p-p)= 800 mV
blackto white transition in
1 pixel with98.5%
Virecovery
8−−ns
th(IN;SHP) CDS input hold time (pin IN)
compared to control pulse
SHP
see Figure 3 and 44−−ns
th(IN;SHD) CDS input hold time (pin IN)
compared to control pulse
SHD
see Figure 3 and 44−−ns
Amplifier
DRPGA PGA dynamic range −24 −dB
∆GPGA PGA gain step 0.08 0.10 0.12 dB
Analog-to-Digital Converter(ADC)
DNL differential non linearity fpix = 30 MHz; ramp input −±0.5 ±0.9 LSB
Total chain characteristics (CDS+ PGA + ADC)
fpix(max) maximum pixel frequency 30 −−MHz
Table 6: Characteristics
…continued
V
CCA
=V
CCD
= 3.0 V; VCCO
= 2.7 V; fpix
= 30 MHz; Tamb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit