Quatech RS-422/485, MPA-200/300 user manual Configuration Register

8 CONFIGURATION REGISTER

The MPA-200 is equipped with an onboard register used for configuring informa- tion such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed description of the configuration register. The address of this register is Base+5. Table 13 details the bit definitions of the configuration register.

Table 13		Configuration Register - Read/Write
	D7		D6	D5	D4	D3	D2	D1	D0
	0		0	INTS1	INTS0	DMREN	DMTEN	RXSRC	TXSRC

D7-D6 Reserved, always 0.

D5-D4 - INTS1, INTS0, INTERRUPT SOURCE AND ENABLE BITS: These two bits determine the source of the interrupt. The three sources are interrupt on terminal count (INTTC), interrupt from the SCC (INTSCC), and interrupt on Test Mode (INTTM). When the source is set, that interrupt becomes enabled. Below is the mapping for these bits.

INTS1	INTS0	Interrupt
0	0	Interrupts Disabled
0	1	INTTC
1	0	INTSCC
1	1	INTTM

D3 -DMREN, DMA ON RECEIVE ENABLE:

When set (logic 1), the signal from the SCC’s receive DMA source is passed on to the selected ISA bus DRQ. When cleared (logic 0), the SCC cannot drive the receive request signal onto the ISA bus DRQ.

D2 -DMTEN, DMA ON TRANSMIT ENABLE:

When set (logic 1), the signal from the SCC’s transmit DMA source is passed on to the selected ISA bus DRQ. When cleared (logic 0), the SCC cannot drive the transmit request signal onto the ISA bus DRQ.

21 Quatech Inc., MPA-200/300 Manual