clock (TCLK) and the RTXC pin for its receive clock (RCLK). Programming of the clocks should be done before enabling the receiver, transmitter, BRG, or DPLL.
Table 3 SCC write register description.
WR0 | Command Register, Register Pointer, CRC initialization, resets for |
| various modes |
WR1 | Interrupt control, Wait/DMA request control |
WR2 | Interrupt vector |
WR3 | Receiver initialization and control |
WR4 | Transmit/Receive miscellaneous parameters and codes, clock rate, |
| stop bits, parity |
WR5 | Transmitter initialization and control |
|
|
WR6 | Sync character (1st byte) or SDLC address field |
|
|
WR7 | Sync character (2nd byte) or SDLC Flag |
WR7' | HDLC enhancement register |
WR8 | Transmit buffer |
WR9 | Master interrupt control and reset |
|
|
WR10 | Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM |
| coding, CRC reset |
WR11 | Clock mode and source control |
WR12 | Lower byte of baud rate time constant |
WR13 | Lower byte of baud rate time constant |
WR14 | Miscellaneous control bits: baud rate generator, DPLL control, auto |
| echo |
WR15 | External/Status interrupt control |
Quatech Inc., | 8 |
