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| TABLE OF CONTENTS |
|
1 INTRODUCTION | 2 | |
2 HARDWARE INSTALLATION | 4 | |
3 SCC GENERAL INFORMATION | 5 | |
3.1 | Accessing the registers | 6 |
3.2 Baud Rate Generator Programming | 9 | |
3.3 SCC Data Encoding Methods | 10 | |
4 JUMPER BLOCK CONFIGURATIONS | 11 | |
4.1 | J4 - Interrupt Configuration | 11 |
4.2 | J5 & J6 - Interrupt Level Selection | 11 |
4.3 | J10 - Transmit DMA Channel Selection | 12 |
4.4 | J11 - Receive DMA Channel Selection | 13 |
4.5 | J7 - Line Driver Control Selection | 13 |
4.6 J8 - SYNCA to RLEN control | 14 | |
5 ADDRESSING | 15 | |
6 INTERRUPTS | 17 | |
7 DIRECT MEMORY ACCESS | 18 | |
7.1 | Using Terminal Count to Generate an Interrupt | 20 |
8 CONFIGURATION REGISTER | 21 | |
9 COMMUNICATIONS REGISTER | 23 | |
10 DTE / DCE Configuration | 25 | |
10.1 DTE Configuration | 26 | |
10.2 DCE Configuration | 27 | |
11 EXTERNAL CONNECTIONS | 29 | |
11.1 | 32 | |
11.2 | 32 | |
12 DEFINITION OF INTERFACE SIGNALS | 33 | |
13 SPECIFICATIONS | 37 |
Quatech Inc.,