Quatech MPA-200/300, RS-422/485 user manual D1 -RECEIVER Enable, D0 -TRANSMITTER Enable

D3 -RECEIVE CLOCK ENABLE (DCE only):

When set (logic 1), this bit allows the DCE to transmit its receive clock (RCLK). When cleared (logic 0), the DCE receives its RCLK. Since a DTE can only receive its RCLK, writing to this bit has no effect on a DTE.

D2 -TRANSMIT CLOCK ENABLE (DTE only):

When set (logic 1), this bit allows the DTE to transmit its transmit clock (TCLK). When cleared (logic 0), the DTE receives its TCLK. Since a DCE can only transmit its TCLK, writing to this bit has no effect on a DCE.

D1 -RECEIVER ENABLE:

If J7 is configured to allow the Communications Register to control the MPA-200’s receivers (see Table 10 on page 14) then when D1 is set (logic 1) the receivers are enabled and when D1 is cleared (logic 0) the receivers are disabled.

D0 -TRANSMITTER ENABLE:

If J7 is configured to allow the Communications Register to control the MPA-200’s receivers (see Table 10 on page 14) then when D0 is set (logic 1) the transmitters are enabled and when D0 is cleared (logic 0) the transmitters are disabled.

Quatech Inc., MPA-200/300 Manual 24