of the SCC, a DMA request is generated. The DMA controller then writes the data from the SCC into memory.
Programming for DMA request on both transmit and receive is simply a combina- tion of the two. There are three possible configurations that can be used, depend- ing on the sources selected. The first configuration available uses the W/REQA pin of channel A for DMA request on receive, and the DTR/REQA pin of channel A for DMA request on transmit. This is done by setting bit D0 and clearing bit D1 of the configuration register. The second configuration uses the DTR/REQA pin for DMA request on transmit, and the W/REQB pin for DMA request on receive. This is done by setting both D0 and D1 of the configuration register. These two configurations give users an optional way of performing DMA requests on both transmit and receive. Otherwise, the third configuration should be used. This configuration uses the W/REQA pin of channel A for DMA request on trans- mit, and the W/REQB pin of channel B for DMA request on receive. This is done by clearing bit D0 and setting bit D1 of the configuration register. Figure 3 shows a block diagram of the DMA circuitry on the
When using the channel A DTR/REQ pin for transmit DMA the SCC must be programmed so that the request release timing of this pin is identical to the WAIT/REQ timing. This is done by setting bit D4 of write register 7 prime.
NOTE:
Even though the W/REQA pin can be used for both DMA request on transmit and receive, obviously it cannot be used for both simultaneously. Therefore, bits D0 and D1 of the configuration register should never be cleared at the same time while bits D2 and D3 are both set. This situation may result in damage to the system.
19 | Quatech Inc., |
