ATAPI Interface |
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| Chapter 5 |
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53 | Field Validity | 0002h | Fields |
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Current Cylinder/Heads/Sectors | 0000h | Unsupported |
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Current Capacity | 0000h | Unsupported |
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59 | Reserved | 0000h | — |
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User Addressable Sectors | 0000h | Unsupported |
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62 | Single Word DMA Mode | 0407h | Selected DMA mode 2 (Upper Byte), |
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| DMA modes 2,1,0 Supported. |
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63 | Multi Word DMA Mode | 0407h | Selected DMA mode 2 (Upper Byte) |
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| DMA modes 2, 1, 0 supported. |
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64 | Enhanced PIO Mode | 0003h | PIO Mode 3 and 4 Supported |
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65 | Minimum Multi Word DMA Cycle Time | 0078h | Mode 2 (120 nanoseconds) |
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66 | Recommended Multi Word DMA Cycle | 0078h | Mode 2 (120 nanoseconds) |
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67 | Minimum PIO Cycle Time w/o IORDY | 0078h | Mode 4 (120 nanoseconds) |
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68 | Minimum PIO Cycle Time with IORDY | 0078h | Mode 4 (120 nanoseconds) |
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Reserved/Vendor Unique | 0000h | — |
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ATAPI Packet Command (A0h)
Before issuing the ATAPI Packet command, the host writes to the Byte Count register (high and low) the maximum/preferred number of bytes to be transferred in a single PIO DRQ. For Data Transfer commands (READ and WRITE), this value is assumed to be greater than or equal to 512 and is ignored.
ATAPI Soft Reset (08h)
The ATAPI Soft Reset command performs a complete microprocessor reset. Current physical and logical position is lost, and if a tape is present, a LOAD sequence is performed, resulting in a Ready at BOP0 condition (with Unit Attn).
The DSC is set to 1 before the BSY bit is cleared.
STT8000A Product Manual | Page 37 |
