Interface Description
PCM Interface
Overview
PCM Pulse Code Modulation is a standard method used to digitise human voice
Maximum of one SCO connection is possible using the PCM interface
Further SCO channels must use the HCI protocol layer
Data format is 13 bit linear PCM
Description
Pulse Code Modulation (PCM) is the standard method used to digitise human voice patterns for transmission over digital communication channels. Through its PCM interface, SieMo provides hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications.
SieMo offers a
SieMo S50037 Data Book PRELIMINARILY
Generic PCM Interface
For a generic PCM interface there is one master and one slave device. The master generates the clock and synchronisation signals. The sync signal identifies the start of the sample data and has an 8kHz period. There are two types of frame sync: long and short. In long frame sync mode PCM_SYNC going high indicates the first (and most significant) bit of the sample. It must remain high for at least two clock cycles, but this can be longer. In short frame sync MSB start is signalled by sync going low (normally it only goes high for one clock cycle).
The clock runs at a higher rate than sync: at least 8 x bits_per_sample MHz, although higher rates are common. The sample resolution is 13 bits/sample, uncompressed. Several Motorola CODECs allow their output gain to be controlled via the addition of three extra data bits after the audio data. SieMo supports this feature, effectively raising the bits per sample to 16. Data from both the master and slave is clocked out on the rising clock edge and sampled on the falling edge. Master mode is the default setting. In master mode SieMo generates a 256kHz clock signal (PCM_CLK) and the 8kHz, long format synchronisation signal (PCM_SYNC). Short frame sync is not supported. See PCM Timing Diagrams for more information.
Slave mode is selected by setting a Persistent Store value. In slave mode SieMo clocks output data on the rising edge of the received clock signal and samples incoming data on the falling edge. The incoming clock frequency should be between 128kHz and 512kHz. (Note that 128kHz is 8 x 16 kHz, therefore the absolute minimum possible frequency for the 8ksamples/sec and 16bits/sample (13 audio data plus three gain data). The frame sync must be long format. Short format is not supported (see SSI Mode and Timing Diagrams in this section for more information).
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