Silicon Image SSD-DXXX(I)-4210 manual True IDE Multiword DMA Read/Write Access Timing

ELECTRICAL SPECIFICATION					SSD-DXXX(I)-4210 DATA SHEET
	Table 12: True IDE Multiword DMA Read/Write Access Timing
	Symbol	Item	Mode 0 Mode 1		Mode 2	Mode 3 Mode 4 Note			Units
	tO	Cycle Time (minimum)	480	150	120	100	80	1	ns
	tD	-IORD/-IOWR	215	80	70	65	55	1	ns
		Asserted Width
		(minimum)
	tE	-IORD Data Access	150	60	50	50	45	-	ns
		(maximum)
	tF	-IORD Data Hold	5	5	5	5	5	-	ns
		(minimum)
	tG	-IORD/-IOWR Data	100	30	20	15	10	-	ns
		Setup (minimum)
	tH	-IOWR Data Hold	20	15	10	5	5	-	ns
		(minimum)
	tl	DMACK to –IORD/-	0	0	0	0	0	-	ns
		IOWR Setup
		(minimum)
	tJ	-IORD / -IOWR to -	20	5	5	5	5	-	ns
		DMACK Hold
		(minimum)
	tKR	-IORD Negated Width	50	50	25	25	20	1	ns
		(minimum)
	tKW	-IOWR Negated Width	215	50	25	25	20	1	ns
		(minimum)
	tLR	-IORD to DMARQ	120	40	35	35	35	-	ns
		Delay (maximum)
	tLW	-IOWR to DMARQ	40	40	35	35	35	-	ns
		Delay (maximum)
	tM	CS(1:0) Valid to –	50	30	25	10	5	-	ns
		IORD / -IOWR
	tN	CS(1:0) Hold	15	10	10	10	10	-	ns
	tZ	-DMACK	20	25	25	25	25	-	ns

Note:

1.The symbol t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the minimum command recovery times or command inactive times for input and output cycles, respectively. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, tD, tKR, and tKW must be met. The minimum total cycle time requirement is greater than the sum of tD and tKR, or tKW for input and output cycles, respectively. This means a host implementation can lengthen either or both of tD and either of tKR and tKW as needed to ensure that t0 is equal to or greater than the value reported in the device’s identify device data.

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4210D-03DSR PAGE 16 FEBRUARY 2, 2009