ELECTRICAL SPECIFICATION

 

 

 

 

 

 

 

SSD-DXXX(I)-4210 DATA SHEET

 

Table 13: UDMA Data Burst Timing Requirements (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Mode 0

 

Mode 1

Mode 2

Mode 3

Mode 4

Comment (see Notes 1 and

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

Max.

Min. Max.

Min. Max.

Min. Max.

2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVS

70

-

 

48

-

30

-

20

-

6

-

Data valid setup time at

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

sender (from data valid until

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STROBE edge) (see Note 4).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVH

6

-

 

6

-

6

-

6

-

6

-

Data valid hold time at sender

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

(from STROBE edge until

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data may become invalid)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Note 4).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tFS

0

230

 

0

200

0

170

0

130

0

120

First STROBE time (for

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

device to first negate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSTROBE from STOP during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a data-in burst).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLI

0

150

 

0

150

0

150

0

100

0

100

Limited interlock time (see

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 3).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tMLI

20

-

 

20

-

20

-

20

-

20

-

Interlock time with minimum

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Note 3).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tUI

0

-

 

0

-

0

-

0

-

0

-

Unlimited interlock time (see

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 3).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAZ

-

10

 

-

10

-

10

-

10

-

10

Maximum time allowed for

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

output drivers to release

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(from asserted or negated).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tZAH

20

-

 

20

-

20

-

20

-

20

-

Minimum delay time required

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

for output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tZAD

0

-

 

0

-

0

-

0

-

0

-

Drivers to assert or negate

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

(from released).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tENV

20

70

 

20

70

20

70

20

55

20

55

Envelope time (from DMACK-

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

to STOP and HDMARDY-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during data-in burst initiation,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and from DMACK to STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during data-out burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

initiation).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSR

-

50

 

-

30

-

20

-

NA

-

NA

STROBE to DMARDY- time

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

(if DMARDY- is negated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

before this long after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STROBE edge, the recipient

 

 

 

 

 

 

 

 

 

 

 

 

 

 

receives no more than one

 

 

 

 

 

 

 

 

 

 

 

 

 

 

additional data word).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRFS

-

75

 

-

70

-

60

-

60

-

60

Ready-to-final STROBE time

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

(no STROBE edges are sent

 

 

 

 

 

 

 

 

 

 

 

 

 

 

this long after negation of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMARDY-).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRP

160

-

 

125

-

100

-

100

 

100

-

Minimum time to assert STOP

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

or negate DMARQ.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tIORDYZ

-

20

 

-

20

-

20

-

20

-

20

Maximum time before

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

releasing IORDY.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tZIORDY

0

-

 

0

-

0

-

0

-

0

-

Minimum time before driving

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

STROBE (see note 5).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACK

20

-

 

20

-

20

-

20

-

20

-

Setup and hold times for

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

DMACK- (before assertion or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

negation).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SILICONSYSTEMS PROPRIETARY

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4210D-03DSR

PAGE 25

FEBRUARY 2, 2009

Page 34
Image 34
Silicon Image SSD-DXXX(I)-4210 manual Min Max Min. Max

SSD-DXXX(I)-4210 specifications

The Silicon Image SSD-DXXX(I)-4210 is a cutting-edge solid-state drive designed for high-performance computing applications. Designed to cater to both consumer and enterprise markets, the SSD-DXXX(I)-4210 stands out for its robust features and advanced technologies, making it an ideal choice for those who demand reliability and speed.

One of the key features of the SSD-DXXX(I)-4210 is its exceptional read and write speeds. With read speeds reaching up to 550 MB/s and write speeds up to 520 MB/s, the drive significantly reduces loading times for applications and files. This performance is enhanced by the integrated SMI controller, which optimizes data transfer and minimizes latency, ensuring seamless multitasking and efficient workflows.

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