ELECTRICAL SPECIFICATION SSD-DXXX(I)-4210 DATA SHEET
SILICONSYSTEMS PROPRIETARY
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4210D-03DSR PAGE 25 FEBRUARY 2, 2009

tDVS 70 - 48 - 30 - 20 - 6 - Data valid setup time at
sender (from data valid until
STROBE edge) (see Note 4).
ns
tDVH 6 - 6 - 6 - 6 - 6 - Data valid hold time at sender
(from STROBE edge until
data may become invalid)
(see Note 4).
ns
tFS 0 230 0 200 0 170 0 130 0 120 First STROBE time (for
device to first negate
DSTROBE from STOP during
a data-in burst).
ns
tLI 0 150 0 150 0 150 0 100 0 100 Limited interlock time (see
Note 3).
ns
tMLI 20 - 20 - 20 - 20 - 20 - Interlock time with minimum
(see Note 3).
ns
tUI 0 - 0 - 0 - 0 - 0 - Unlimited interlock time (see
Note 3).
ns
tAZ - 10 - 10 - 10 - 10 - 10 Maximum time allowed for
output drivers to release
(from asserted or negated).
ns
tZAH 20 - 20 - 20 - 20 - 20 - Minimum delay time required
for output.
ns
tZAD 0 - 0 - 0 - 0 - 0 - Drivers to assert or negate
(from released).
ns
tENV 20 70 20 70 20 70 20 55 20 55 Envelope time (f rom DMACK-
to STOP and HDMARDY-
during data-in burst initiation,
and from DMACK to STOP
during data-out burst
initiation).
ns
tSR - 50 - 30 - 20 - NA - NA STROBE to DMARDY- time
(if DMARDY- is negated
before this long after
STROBE edge, the recipient
receives no more than one
additional data word).
ns
tRFS - 75 - 70 - 60 - 60 - 60 Ready-to-final STROBE time
(no STROBE edges are sent
this long after negation of
DMARDY-).
ns
tRP 160 - 125 - 100 - 100 100 - Minimum time to assert STOP
or negate DMARQ.
ns
tIORDYZ - 20 - 20 - 20 - 20 - 20 Maximum time before
releasing IORDY.
ns
tZIORDY 0 - 0 - 0 - 0 - 0 - Minimum time before driving
STROBE (see note 5).
ns
tACK 20 - 20 - 20 - 20 - 20 - Setup and hold times for
DMACK- (before assertion or
negation).
ns
Table 13: UDMA Data Burst Timing Requirements (Continued)
Symbol Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Comment (see Notes 1 and
2) Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.