Silicon Image SSD-DXXX(I)-4210 - page 72

ATA COMMAND BLOCK AND SET DESCRIPTION SSD-DXXX(I)-4210 DATA SHEET

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4210D-03DSR PAGE 63 FEBRUARY 2, 2009

Standby — 96h, E2h

When the Standby command is issued by the host, it transitions the device into

standby mode. If the Sector Count register is set to a value other than 0h, the

Auto Powerdown function is enabled and the device returns to Idle mode.

Table 49: Standby — 96h, E2h

Register D7D6D5D4D3D2D1D0

Feature X

Sector Count Timer Count (5ms x Timer Count)

Sector Number X

Cylinder Low X

Cylinder High X

Drive Head X X X Drive X

Command 96h or E2h

Contents

Main O F D ATA S SSD-DXXX(I)-4210 SILICONDRIVE EP 2.5" PATA DRIVE REVISION HISTORY T ABLE OF C Page Page L IST OF F LIST OF TABLES Page Page P HYSICAL S P HYSICAL D P IN L JUMPER SETTINGS P RODUCT S S YSTEM P S YSTEM P OWER R R P ROJECTED O PERATIONAL L IFE S P RODUCT C APACITY S E NVIRONMENTAL S E LECTRICAL S P IN A S IGNAL D Page Page Page A BSOLUTE M AXIMUM R DC C AC C 4210D-03DSR PAGE 14 FEBRUARY 2, 2009 Table 11: True IDE PIO Mode Read/Write Access Timing ttt tt t t Table 12: True IDE Multiword DMA Read/Write Access Timing 4210D-03DSR PAGE 17 FEBRUARY 2, 2009 Figure 6: Initiating a UDMA Data-In Burst and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. 4210D-03DSR PAGE 18 FEBRUARY 2, 2009 t DMARQ DMACK- STOP Figure 9: Device Terminating a UDMA Data-In Burst and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 4210D-03DSR PAGE 20 FEBRUARY 2, 2009 Figure 10: Host Terminating a UDMA Data-In Burst and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 4210D-03DSR PAGE 21 FEBRUARY 2, 2009 Figure 11: Initiating a UDMA Data-Out Burst Page 4210D-03DSR PAGE 23 FEBRUARY 2, 2009 Figure 14: Host Terminating a UDMA Data-Out Burst 4210D-03DSR PAGE 24 FEBRUARY 2, 2009 Figure 15: Device Terminating a UDMA Data-Out Burst 4210D-03DSR PAGE 25 FEBRUARY 2, 2009 Table 13: UDMA Data Burst Timing Requirements (Continued) 4210D-03DSR PAGE 26 FEBRUARY 2, 2009 ATA AND TRUE IDE REGISTER DECODING TASK FILE REGISTER SPECIFICATION ATA R D ATA R E RROR R F EATURE R S ECTOR C OUNT R S ECTOR N UMBER R C YLINDER L OW R C YLINDER H IGH R D RIVE /H EAD R STATUS REGISTER C OMMAND R A LTERNATE S TATUS R D EVICE C ONTROL R D EVICE A DDRESS R ATA C OMMAND BLOCK AND SET DESCRIPTION ATA COMMAND SET Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page SALES AND SUPPORT PART NUMBERING N P ART N R O HS 6 OF 6 P RODUCT L ABELING P B -F REE I DENTIFICATION L S AMPLE L RELATED DOCUMENTATION SSD-DXXX(I)-4210 DATA SHEET 4210D-03DSR PAGE 79 FEBRUARY 2, 2009 RELATED DOCUMENTATION Table 66: Related Documentation SiliconDrive EP Application-Specific Technology Description Document Number