Silicon Image SSD-DXXX(I)-4210 4210D-03DSR PAGE 26 FEBRUARY 2, 2009

ELECTRICAL SPECIFICATION SSD-DXXX(I)-4210 DATA SHEET
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4210D-03DSR PAGE 26 FEBRUARY 2, 2009
tSS 50 - 50 - 50 - 50 - 50 - Time from STROBE edge to
negation of DMARQ or
assertion of STOP (when the
sender terminates a burst).
ns
Notes:
1. Timing parameters are measured at the connector of the sender or receiver to which the parameter applies.
Both STROBE and DMARDY- timing measurements are taken at the sender’s connector.
Example: For example, the sender stops generating STROBE edges tRFS after the negation of DMARDY-.
2. All timing measurement switching points (low-to-high and high-to-low) are taken at 1.5V.
3. The symbols tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks (i.e., either the sender
or recipient is waiting for the other to respond with a signal before proceeding). The symbol tUI is an unlimited
interlock that has no maximum time value, tMLI is a limited time-out that has a defined minimum, and tLI is a
limited time-out that has a defined maximum.
4. The test load for tDVS and tDVH are a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH
are met for all capacitive loads from 15pF to 40pF where all signals have the same capacitive load value.
5. The symbol tZIORDY may be greater than tENV since the device has a pull-up on IORDY- giving it a known state
when released.
Table 13: UDMA Data Burst Timing Requirements (Continued)
Symbol Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Comment (see Notes 1 and
2) Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.