Si5351A/B/C

7. Register Map Summary

The following is a summary of the register map used to read status, control, and configure the Si5351.

Register

7

6

 

5

4

3

2

 

1

0

 

0

SYS_INIT

LOL_B

 

LOL_A

LOS

 

 

 

REVID[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

1

SYSCAL_

LOS_B_

 

LOL_A_

LOS_

 

 

 

 

 

 

 

 

STKY

STKY

 

STKY

STKY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

SYSCAL_

LOS_B_

 

LOL_A _

LOS_

 

 

 

 

 

 

 

 

MASK

MASK

 

MASK

MASK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

CLK7_EN

CLK6_EN

 

CLK5_EN

CLK4_EN

CLK3_EN

CLK2_EN

 

CLK1_EN

CLK0_EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4–8

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

OEB_CLK7

OEB_CLK6

 

OEB_CLK5

OEB_CLK4

OEB_CLK3

OEB_CLK2

 

OEB_CLK1

OEB_CLK0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10–14

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

0

0

 

0

0

PLLB_SRC

PLLA_SRC

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

CLK0_PDN

MS0_INT

 

MS0_SRC

CLK0_INV

CLK0_SRC[1:0]

 

CLK0_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

17

CLK1_PDN

MS1_INT

 

MS1_SRC

CLK1_INV

CLK1_SRC[1:0]

 

CLK1_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

18

CLK2_PDN

MS2_INT

 

MS2_SRC

CLK2_INV

CLK2_SRC[1:0]

 

CLK2_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

19

CLK3_PDN

MS3_INT

 

MS3_SRC

CLK3_INV

CLK3_SRC[1:0]

 

CLK3_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

20

CLK4_PDN

MS4_INT

 

MS4_SRC

CLK4_INV

CLK4_SRC[1:0]

 

CLK4_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

21

CLK5_PDN

MS5_INT

 

MS5_SRC

CLK5_INV

CLK5_SRC[1:0]

 

CLK5_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

22

CLK6_PDN

FBA_INT

 

MS6_SRC

CLK6_INV

CLK6_SRC[1:0]

 

CLK6_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

23

CLK7_PDN

FBB_INT

 

MS6_SRC

CLK7_INV

CLK7_SRC[1:0]

 

CLK7_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

24

CLK3_DIS_STATE

 

CLK2_DIS_STATE

CLK1_DIS_STATE

 

CLK0_DIS_STATE

 

 

 

 

 

 

 

 

 

25

CLK7_DIS_STATE

 

CLK6_DIS_STATE

CLK5_DIS_STATE

 

CLK4_DIS_STATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26–41

 

 

PLL, MultiSynth, and output clock delay offset Configuration Registers.

 

 

 

 

 

 

Use ClockBuilder Desktop Software to Determine These Register Values.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

 

 

 

 

MS0_P3[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

43

 

 

 

 

MS0_P3[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

 

 

R0_DIV[2:0]

 

 

 

 

MS0_P1[17:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

45

 

 

 

 

MS0_P1[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

 

 

 

 

MS0_P1[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

47

 

MS0_P3[19:16]

 

 

MS0_P2[19:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

 

 

 

 

MS0_P2[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

 

 

 

 

MS0_P2[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

 

MS1_P3[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

 

 

 

 

MS1_P3[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

 

 

 

R1_DIV[2:0]

 

 

 

 

MS1_P1[17:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

53

 

 

 

 

MS1_P1[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54

 

 

 

 

MS1_P1[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

 

MS1_P3[19:16]

 

 

MS1_P2[19:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

 

 

 

 

MS1_P2[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

 

 

 

 

MS1_P2[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

 

 

 

 

MS2_P3[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

 

 

 

 

MS2_P3[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

R2_DIV[2:0]

 

 

 

 

MS2_P1[17:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

61

 

 

 

 

MS2_P1[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

 

 

 

 

MS2_P1[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

 

MS2_P3[19:16]

 

 

MS2_P2[19:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

 

 

 

 

MS2_P2[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

MS2_P2[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preliminary Rev. 0.95

23

Page 23
Image 23
Silicon Laboratories SI5351A/B/C specifications Register Map Summary

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.