Silicon Laboratories SI5351A/B/C - page 38

Si5351A/B/C

38 Preliminary Rev. 0.95

Reset value = 0000 0000

Reset value = 0000 0000

Register 24. CLK3–0 Disable State

BitD7D6D5D4D3D2D1D0

Name CLK3_DIS_STATE CLK2_DIS_STATE CLK1_DIS_STATE CLK0_DIS_STATE

Type R/W R/W R/W R/W

Bit Name Function

7:0 CLKx_DIS_STATE Clock x Disable State.

Where x = 0, 1, 2, 3. These 2 bits determine the state of the CLKx output when dis-

abled. Individual output clocks can be disabled using register Output Enable Con-

trol located at address 3. Outputs are also disabled using the OEB pin.

00: CLKx is set to a LOW state when disabled.

01: CLKx is set to a HIGH state when disabled.

10: CLKx is set to a HIGH IMPEDANCE state when disabled.

11: CLKx is NEVER DISABLED.

Register 25. CLK7–4 Disable State

BitD7D6D5D4D3D2D1D0

Name CLK7_DIS_STATE CLK6_DIS_STATE CLK5_DIS_STATE CLK4_DIS_STATE

Type R/W R/W R/W R/W

Bit Name Function

7:0 CLKx_DIS_STATE Clock x Disable State.

Where x = 4, 5, 6, 7. These 2 bits determine the state of the CLKx output when dis-

abled. Individual output clocks can be disabled using register Output Enable Con-

trol located at address 3. Outputs are also disabled using the OEB pin.

00: CLKx is set to a LOW state when disabled.

01: CLKx is set to a HIGH state when disabled.

10: CLKx is set to a HIGH IMPEDANCE state when disabled.

11: CLKx is NEVER DISABLED.

Contents

Main Si5351A/B/C I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR + VCXO Functional Block Diagram Features Applications Description Page Si5351A/B/C T ABLE OF C Section Page 1. Electrical Specifications Table 1. Recommended Operating Conditions Table 2. DC Characteristics Si5351A/B/C Table 3. AC Characteristics Table 4. Input Clock Characteristics Table 5. Output Clock Characteristics Table 6. Crystal Requirements Table 7. I2C Specifications (SCL,SDA)1 Table 8. Thermal Characteristics Table 9. Absolute Maximum Ratings Preliminary Rev. 0.95 9 2. Detailed Block Diagrams Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices Si5351A 8-Output Si5351A 3-Output Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices Si5351B 20-QFN, 24-QSOP Si5351C 3. Functional Description Figure 3. Si5351 Block Diagram Figure 4. External XTAL with Optional Load Capacitors 3.1. Input Stage 3.2. Synthesis Stages Figure 5. Using the Si5351 as a Multi-Output VCXO 3.3. Output Stage 3.4. Spread Spectrum Figure 6. Available Spread Spectrum Profiles 3.5. Control Pins (OEB, SSEN) 4. I2C Interface Figure 7. I2C and Control Signals Figure 8. Si5351 I2C Slave Address Figure 9. I2C Write Operation Figure 10. I2C Read Operation 5. Configuring the Si5351 Figure 11.Si5351 Memory Configuration 5.1. Writing a Custom Configuration to RAM Page 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs XA XB CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs Si5351C CLKIN Si5351B VC 5.6. Replacing a Crystal with a Clock The Si5351 can be driven with a clock signal through the XA input pin. Figure 16. Si5351 Driven by a Clock Signal 5.7. HCSL Compatible Outputs Figure 17. Si5350C Output is HCSL Compatible 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.6. Trace Characteristics Figure 18.Recommended Trace Characteristics with 8 mA Drive Strength Setting Note: 7. Register Map Summary Page 8. Register Descriptions Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Si5351A/B/C Page Page Page Page Page Page Page Page 62 Preliminary Rev. 0.95 9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Table 10. Si5351A Pin Descriptions SSEN 6 12 I Spread spectrum enable. High = enabled, Low = disabled. 1. 2. Si5351A 20-QFN Top View 10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Table 11. Si5351B Pin Descriptions SSEN 6 12 I Spread spectrum enable. High = enabled, Low = disabled. *Note: *Note: Si5351B 20-QFN Top View 11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Table 12. Si5351C Pin Descriptions CLKIN 6 12 I PLL clock input. Notes: 1. 2. Si5351C 20-QFN Top View 12. Si5351A Pin Descriptions (10-Pin MSOP) Table 13. Si5351A 10-MSOP Pin Descriptions Si5351A 10-MSOP Top View 13. Ordering Information Si535X EVB Si5351X XX Figure 19. Device Part Numbers Figure 20. Si5351A/B/C Evaluation Kit A 14. Package Outline (24-Pin QSOP) Table 14. 24-QSOP Package Dimensions 15. Package Outline (20-Pin QFN) Table 15. Package Dimensions 16. Package Outline (10-Pin MSOP) Table 16. 24-QSOP Package Dimensions DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.9 Revision 0.9 to Revision 0.95 Page 72 Preliminary Rev. 0.95 CONTACT INFORMATION Silicon Laboratories Inc.