Package Outline 10-Pin Msop, Ddd | Silicon Laboratories SI5351A/B/C

Si5351A/B/C

16. Package Outline (10-Pin MSOP)

Table 16. 24-QSOP Package Dimensions

Dimension	Min	Nom	Max
A	—	—	1.10
A1	0.00	—	0.15
A2	0.75	0.85	0.95
b	0.17	—	0.33
c	0.08	—	0.23
D		3.00 BSC
E		4.90 BSC
E1		3.00 BSC
e		0.50 BSC
L	0.40	0.60	0.80
L2		0.25 BSC
q	0	—	8
aaa	—	—	0.20
bbb	—	—	0.25
ccc	—	—	0.10
ddd	—	—	0.08

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Preliminary Rev. 0.95

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SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.

Contents

Functional Block Diagram FeaturesApplications Description Si5351A/B/C Table of Contents DC Characteristics Electrical SpecificationsParameter Symbol Test Condition Min Typ Max Unit Recommended Operating Conditions Input Clock Characteristics AC CharacteristicsVcxo Specifications Si5351B only Parameter Symbol Test Condition Min Typ Max Units Output Clock Characteristics Parameter Symbol Min Typ Max UnitCrystal Requirements1,2 I2C Specifications SCL,SDA1 Thermal CharacteristicsParameter Symbol Test Condition Package Value Unit Absolute Maximum Ratings1 Parameter Symbol Test Condition Value Unit Block Diagrams of 3-Output and 8-Output Si5351A Devices Detailed Block Diagrams Block Diagrams of Si5351B and Si5351C 8-Output Devices Functional Description Input StageCrystal Inputs XA, XB Output Stage Synthesis StagesExternal Clock Input Clkin Voltage Control Input VC Output Enable OEB Control Pins OEB, SsenSpread Spectrum Enable SSEN-Si5351A and Si5351B only Spread Spectrum I2C Interface I2C and Control Signals I2C Write Operation Configuring the Si5351 Writing a Custom Configuration to RAMPower-Up I2C Programming Procedure Replacing Crystals and Crystal Oscillators Si5351 Application Examples Replacing Crystals, Crystal Oscillators, and PLLs Replacing Crystals, Crystal Oscillators, and VCXOsSi5351B Si5351C Hcsl Compatible Outputs Replacing a Crystal with a Clock Design Considerations Trace Characteristics Register Register Map Summary CLK0PHOFF70 Register Descriptions Register 1. Interrupt Status Sticky Clkin Loss Of Signal Sticky Bit Si5351C OnlySystem Calibration Status Sticky Bit Pllb Loss Of Lock Status Sticky Bit Register 2. Interrupt Status Mask Clkin Loss Of Signal Mask Si5351C OnlySystem Initialization Status Mask Pllb Loss Of Lock Status Mask Output Disable for CLKx Register 3. Output Enable ControlRegister 9. OEB Pin Enable Control OEB pin enable control of CLKx Pllbsrc Register 15. PLL Input Source MultiSynth 0 Integer Mode Clock 0 Power DownRegister 16. CLK0 Control Bit Name Function MultiSynth 1 Integer Mode Clock 1 Power DownRegister 17. CLK1 Control MultiSynth Source Select for CLK1 MultiSynth 2 Integer Mode Clock 2 Power DownRegister 18. CLK2 Control MultiSynth Source Select for CLK2 MultiSynth 3 Integer Mode Clock 3 Power DownRegister 19. CLK3 Control MultiSynth Source Select for CLK3 MultiSynth 4 Integer Mode Clock 4 Power DownRegister 20. CLK4 Control MultiSynth Source Select for CLK4 MultiSynth 5 Integer Mode Clock 5 Power DownRegister 21. CLK5 Control MultiSynth Source Select for CLK5 FBA MultiSynth Integer Mode Clock 7 Power DownRegister 22. CLK6 Control MultiSynth Source Select for CLK6 Register 23. CLK7 Control FBB MultiSynth Integer ModeMultiSynth Source Select for CLK7 Output Clock 7 Invert Bit Name Function CLKxDISSTATE Clock x Disable State Register 24. CLK3-0 Disable StateRegister 25. CLK7-4 Disable State Clock x Disable State MS0P3158 Type Reset value Register 42. Multisynth0 Parameters BitMS0P370 Register 44. Multisynth0 Parameters Bit R0 Output DividerRegister 45. Multisynth0 Parameters Bit MS0P170 Register 46. Multisynth0 Parameters BitMS0P31916 MS0P21916 MS0P2158 MS0P270 Register 49. Multisynth0 Parameters BitMS1P3158 MS1P370 Register 52. Multisynth1 Parameters Bit R1 Output DividerRegister 53. Multisynth1 Parameters Bit MS1P31916 MS1P21916 Register 54. Multisynth1 Parameters Bit Name MS1P170 MS1P270 Register 57. Multisynth1 Parameters Bit R2 Output Divider Register 60. Multisynth2 Parameters BitMultisynth2 Parameter Register 61. Multisynth2 Parameters Bit MS2P31916 MS2P21916 Register 62. Multisynth2 Parameters Bit Name MS2P170 MS2P270 Register 65. Multisynth2 Parameters BitMS3P3158 MS3P370 Register 68. Multisynth3 Parameters Bit R3 Output DividerRegister 69. Multisynth3 Parameters Bit MS3P31916 MS3P21916 Register 70. Multisynth3 Parameters Bit Name MS3P170 MS3P270 Register 73. Multisynth3 Parameters BitMS4P3158 MS4P370 Register 76. Multisynth4 Parameters Bit R4 Output DividerRegister 77. Multisynth4 Parameters Bit MS4P31916 MS4P21916 Register 78. Multisynth4 Parameters Bit Name MS4P170 MS4P270 Register 81. Multisynth4 Parameters BitMS5P3158 MS5P370 Register 84. Multisynth5 Parameters Bit R5 Output DividerRegister 85. Multisynth5 Parameters Bit MS5P31916 MS5P21916 Register 86. Multisynth5 Parameters Bit Name MS5P170 MS5P270 Register 89. Multisynth5 Parameters BitMS6P170 MS7P170 Register 92. Clock 6 and 7 Output Divider Bit R7 Output DividerR6 Output Divider Clock 0 Initial Phase Offset Register 165. CLK0 Initial Phase OffsetRegister 166. CLK1 Initial Phase Offset Clock 1 Initial Phase Offset Clock 3 Initial Phase Offset Register 168. CLK3 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Clock 4 Initial Phase Offset PLLBReset Register 177. PLL ResetPLLAReset Register 183. Crystal Internal Load Capacitance Si5351A Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351A Pin DescriptionsPin Name Pin Number Pin Type Function 20-QFN Si5351B Pin Descriptions 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351C Pin Descriptions 11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351A 10-MSOP Pin Descriptions 12. Si5351A Pin Descriptions 10-Pin MsopPin Number Device Part Numbers Ordering Information Si5351X Qsop Package Dimensions Dimension Min Nom MaxPackage Outline 24-Pin Qsop Package Dimensions Dimension Min NomPackage Outline 20-Pin QFN Ddd Package Outline 10-Pin Msop Revision 0.9 to Revision Revision 0.1 to Revision Si5351A/B/C Contact Information

Silicon Laboratories SI5351A/B/C specifications Package Outline 10-Pin Msop, Ddd

Models: SI5351A/B/C

Si5351A/B/C

16. Package Outline (10-Pin MSOP)

Table 16. 24-QSOP Package Dimensions

Dimension

ddd

SI5351A/B/C specifications