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SMSC LAN8710, LAN8710i, MII 10/100, RMII 10/100 1.3Architectural Overview, 1.3.1Configuration, MAC, RJ45, 10/100, LAN8710, Ethernet, Clock Osc, Crystal or, Transformer

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MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology in a Small Footprint

Datasheet

10/100

MDI

Ethernet

Transformer

RJ45

MAC

LAN8710

MII or

Ethernet

RMII

Transceiver

MODE

LED Status

Crystal or

Clock Osc

Figure 1.1 LAN8710/LAN8710i System Block Diagram

1.3Architectural Overview

The LAN8710/LAN8710i is compliant with IEEE 802.3-2005 standards (MII Pins tolerant to 3.6V) and supports both IEEE 802.3-2005 compliant and vendor-specific register functions. It contains a full- duplex 10-BASE-T/100BASE-TX transceiver and supports 10-Mbps (10BASE-T) operation, and 100- Mbps (100BASE-TX) operation. The LAN8710/LAN8710i can be configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. An option is available to disable the linear regulator to optimize system designs that have a 1.2V power supply available. This allows for the use of a high efficiency external regulator for lower system power dissipation.

1.3.1Configuration

The LAN8710 will begin normal operation following reset, and no register access is required. The initial configuration may be selected with configuration pins as described in Section 5.3.9. In addition, register-selectable configuration options may be used to further define the functionality of the transceiver. For example, the device can be set to 10BASE-T only. The LAN8710 supports both IEEE 802.3-2005 compliant and vendor-specific register functions.

Revision 1.0 (04-15-09)	10	SMSC LAN8710/LAN8710i
	DATASHEET

Contents

PRODUCT FEATURES DATASHEET ORDER NUMBER(S): Reel Size is DATASHEET Table of Contents Page Page List of Figures List of Tables Page 1.1General Terms and Conventions 1.2General Description 1.3Architectural Overview 1.3.1Configuration Page 2.1Package Pin-outDiagram and Signal Table Page 3.1MAC Interface Signals Page 3.2LED Signals 3.3Management Signals 3.4General Signals 3.510/100 Line Interface Signals 3.6Analog Reference 3.7Power Signals 4.1Top Level Functional Architecture 4.2100Base-TXTransmit 4.2.1100M Transmit Data Across the MII/RMII Interface 4.2.24B/5B Encoding 4.2.3Scrambling 4.2.4NRZI and MLT3 Encoding 4.2.5100M Transmit Driver 4.2.6100M Phase Lock Loop (PLL) 4.3100Base-TXReceive 4.3.1100M Receive Input 4.3.2Equalizer, Baseline Wander Correction and Clock and Data Recovery 4.3.3NRZI and MLT-3Decoding 4.3.4Descrambling 4.3.5Alignment 4.3.65B/4B Decoding 4.3.7Receive Data Valid Signal 4.410Base-TTransmit 4.4.110M Transmit Data Across the MII/RMII Interface 4.4.2Manchester Encoding 4.4.310M Transmit Drivers 4.510Base-TReceive 4.5.110M Receive Input and Squelch 4.5.2Manchester Decoding 4.5.310M Receive Data Across the MII/RMII Interface 4.5.4Jabber Detection 4.6MAC Interface 4.6.1MII 4.6.2RMII 4.6.3MII vs. RMII Configuration 4.7Auto-negotiation Page 4.7.1Parallel Detection 4.7.2Re-starting Auto-negotiation 4.7.3Disabling Auto-negotiation 4.7.4Half vs. Full Duplex 4.8HP Auto-MDIXSupport 4.9Internal +1.2V Regulator Disable 4.9.1Disable the Internal +1.2V Regulator 4.9.2Enable the Internal +1.2V Regulator 4.10nINTSEL Strapping and LED Polarity Selection 4.11REGOFF and LED Polarity Selection 4.12PHY Address Strapping 4.13Variable Voltage I/O 4.14Transceiver Management Control 4.14.1Serial Management Interface (SMI) Page Page Page Page Page 5.1SMI Register Format Page Page Page Page Page Page Page 5.2Interrupt Management 5.2.1Primary Interrupt System 5.2.2Alternate Interrupt System 5.3Miscellaneous Functions 5.3.1Carrier Sense 5.3.2Collision Detect 5.3.3Isolate Mode 5.3.4Link Integrity Test 5.3.5Power-Downmodes 5.3.6Reset 5.3.7LED Description 5.3.8Loopback Operation 5.3.8.1Near-endLoopback 10/100 XFMR Digital Ethernet Transceiver 5.3.9Configuration Signals 5.3.9.2Mode Bus – MODE[2:0] 5.3.9.3MII/RMII Mode Selection Page 6.1Serial Management Interface (SMI) Timing 6.2MII 10/100Base-TX/RXTimings 6.2.1MII 100Base-TTX/RX Timings 6.2.1.2100M MII Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER 6.2.2MII 10Base-TTX/RX Timings TX_CLK TXD[3:0] TX_EN 6.3RMII 10/100Base-TX/RXTimings (50MHz REF_CLK IN) 6.3.1RMII 100Base-TTX/RX Timings (50MHz REF_CLK IN) 6.3.1.2100M RMII Transmit Timing (50MHz REF_CLK IN) CLKIN TXD[1:0] Page Page 6.4RMII CLKIN Requirements 6.5Reset Timing 6.6Clock Circuit 7.1DC Characteristics 7.1.1Maximum Guaranteed Ratings 7.1.2Operating Conditions 7.1.3Power Consumption 7.1.4DC Characteristics - Input and Output Buffers Page Page Page 8.1Application Diagram 8.1.1MII Diagram 8.1.2Power Supply Diagram 8.1.3Twisted-PairInterface Diagram 8.2Magnetics Selection