
MII/RMII 10/100 Ethernet Transceiver with HP
Datasheet
The following registers are supported (register numbers are in decimal):
Table 5.20 SMI Register Mapping
REGISTER # | DESCRIPTION | Group |
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0 | Basic Control Register | Basic |
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1 | Basic Status Register | Basic |
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2 | PHY Identifier 1 | Extended |
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3 | PHY Identifier 2 | Extended |
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4 | Extended | |
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5 | Extended | |
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6 | Extended | |
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16 | Silicon Revision Register | |
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17 | Mode Control/Status Register | |
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18 | Special Modes | |
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20 | Reserved | |
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21 | Reserved | |
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22 | Reserved | |
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23 | Reserved | |
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26 | Symbol Error Counter Register | |
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27 | Control / Status Indication Register | |
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28 | Special internal testability controls | |
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29 | Interrupt Source Register | |
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30 | Interrupt Mask Register | |
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31 | PHY Special Control/Status Register | |
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5.1SMI Register Format
The mode key is as follows:
RW = Read/write,
SC = Self clearing,
WO = Write only,
RO = Read only,
LH = Latch high, clear on read of register,
LL = Latch low, clear on read of register,
NASR = Not Affected by Software Reset
X = Either a 1 or 0.
SMSC LAN8710/LAN8710i | 39 | Revision 1.0 |
| DATASHEET |
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