MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology in a Small Footprint

Datasheet

5.2Interrupt Management

The Management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30.

The Interrupt system on the SMSC The LAN8710 has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT.

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative interrupt mode would need to be setup again after a power-up or hard reset.

5.2.1Primary Interrupt System

The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt System is always selected after power-up or hard reset.

To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5.37). Then when the event to assert nINT is true, the nINT output will be asserted.

When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.

Table 5.37 Interrupt Management Table

 

INTERRUPT SOURCE

 

 

EVENT TO

EVENT TO

MASK

 

FLAG

INTERRUPT SOURCE

ASSERT nINT

DE-ASSERT nINT

 

 

 

 

 

 

 

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

Falling 17.1 or

 

 

 

 

 

(Note 5.1)

Reading register 29

 

 

 

 

 

 

 

30.6

29.6

Auto-Negotiation

1.5

Auto-Negotiate

Rising 1.5

Falling 1.5 or

 

 

complete

 

Complete

 

Reading register 29

 

 

 

 

 

 

 

30.5

29.5

Remote Fault

1.4

Remote Fault

Rising 1.4

Falling 1.4, or

 

 

Detected

 

 

 

Reading register 1 or

 

 

 

 

 

 

Reading register 29

 

 

 

 

 

 

 

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

Reading register 1 or

 

 

 

 

 

 

Reading register 29

 

 

 

 

 

 

 

30.3

29.3

Auto-Negotiation

5.14

Acknowledge

Rising 5.14

Falling 5.14 or

 

 

LP Acknowledge

 

 

 

Read register 29

 

 

 

 

 

 

 

30.2

29.2

Parallel Detection

6.4

Parallel

Rising 6.4

Falling 6.4 or

 

 

Fault

 

Detection Fault

 

Reading register 6, or

 

 

 

 

 

 

Reading register 29

 

 

 

 

 

 

or

 

 

 

 

 

 

Re-Auto Negotiate or

 

 

 

 

 

 

Link down

 

 

 

 

 

 

 

30.1

29.1

Auto-Negotiation

6.1

Page Received

Rising 6.1

Falling of 6.1 or

 

 

Page Received

 

 

 

Reading register 6, or

 

 

 

 

 

 

Reading register 29

 

 

 

 

 

 

Re-Auto Negotiate, or

 

 

 

 

 

 

Link Down.

 

 

 

 

 

 

 

Note 5.1 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine.

SMSC LAN8710/LAN8710i

47

Revision 1.0 (04-15-09)

 

DATASHEET