SMSC LAN8710, LAN8710i, MII 10/100, RMII 10/100 4.1Top Level Functional Architecture, 4.2100Base-TXTransmit, 4.2.1100M Transmit Data Across the MII/RMII Interface

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology in a Small Footprint

Datasheet

Chapter 4 Architecture Details

4.1Top Level Functional Architecture

Functionally, the transceiver can be divided into the following sections:

„100Base-TX transmit and receive

„10Base-T transmit and receive

„MII or RMII interface to the controller

„Auto-negotiation to automatically determine the best speed and duplex possible

„Management Control to read status registers and write control registers

		TX_CLK
		(for MII only)		PLL
MAC	Ext Ref_CLK (for RM II only)
	MII 25 Mhz by 4 bits		MII/RMII	25MHz	4B/5B	25MHz by	Scrambler
		or
				by 4 bits	Encoder	5 bits	and PISO
	RMII 50Mhz by 2 bits
	125 M bps Serial	NRZI	NRZI	MLT-3	MLT-3	Tx
		Converter		Converter		Driver

	Magnetics		RJ45		CAT-5
MLT-3		M LT-3		MLT-3

Figure 4.1 100Base-TX Data Path

4.2100Base-TX Transmit

The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.

4.2.1100M Transmit Data Across the MII/RMII Interface

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide 25MHz data.

For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50MHz data.

SMSC LAN8710/LAN8710i	19	Revision 1.0 (04-15-09)
	DATASHEET