Motherboard Description |
|
1-8.3 ECC Memory
ECC memory detects multiple- bit errors and corrects single- bit errors. When ECC memory is installed, the BIOS supports both ECC and non- ECC mode. ECC mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is installed and provides the Setup option for selecting ECC mode. If any non- ECC memory is installed, the Setup option for ECC configuration does not appear and ECC operation is not available.
1-9 CHIPSET
The Intel 440BX PCIset includes a Host- PCI bridge integrated with both an optimized DRM controller and an A. G.P. interface. The I/ O subsystem of the 440BX is based on the PIIX4E, which is a highly integrated PCI- IS A/ IDE Accelerator Bridge. This chipset consists of the Intel 82443BX PCI/ A. G.P. controller (PAC) and the Intel 82371EB PCI/ ISA IDE Xcelerator (PIIX4E) bridge chip.
1-9.1 Intel 82443Bx PCI/A.G.P. Controller (PAC)
The PAC provides bus- control signals, address paths, and data paths for transfers between the processor’s host bus, PCI bus, the A. G.P., and main memory. The PAC features:
lProcessor interface control
ØSupport for processor host bus frequencies of 100 MHz or 66MHz
Ø32- bit addressing
ØDesktop Optimized GTL+ compliant host bus interface
lIntegrated DRAM controller, with support for:
Ø+3.3 Vonly DIMM DRAM configurations
ØUp to four double sided DIMMs
Ø100- MHz or 66 MHz SDRAM
ØDIMM serial presence detect via SMBus interface
Ø16- and 64- Mbit devices with 2K, 4K, and 8K page sizes
ØSDRAM 64- bit data interface with ECC support
ØSymmetrical and asymmetrical DRAM addressing
11
