SOYO SY-7VCA2 user manual PCI Master 0 WS Write Setting Description, PCI Delay Transaction

BIOS Setup Utility SY-7VCA2

CHIPSET FEATURES SETUP (Continued)

CHIPSET FEATURES

PCI Master 0 WS Write

Setting	Description	Note
Disabled
Enabled	When Enabled, writes to the PCI	Default
	bus are executed with zero wait
	states.

PCI Delay Transaction

Disabled

Enabled

The chipset has an embedded 32-bit posted write buffer to support delay Default transactions cycles. Select Enabled

to support compliance with PCI specification version 2.1.

PCI#2 Access #1 Retry

Disabled

Enabled

When disabled, PCI#2 will not be

disconnected until access finishes Default (difault). When enabled, PCI#2 will

be disconnected if max retries are attempted without success.

AGP Master 1 WS Write

Disabled		Default
Enabled	When Enabled, writes to the
	AGP(Accelerated Graphics Port) are
	executed with one wait states.

AGP Master 1 WS Read

Disabled		Default
Enabled	When Enabled, read to the AGP
	(Accelerated Graphics Port) are
	executed with one wait states.

Memory

Parity/ECC

Check

Disabled		Default
Enabled	This item enabled to detect the
	memory parity and Error Checking
	& Correcting.

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