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Motherboard Description |
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⎯Dual copies of MA signals for improved drive
⎯Optional
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⎯
⎯Independent SDRAM control for each bank
⎯Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank)
⎯Four cache lines (16quadwords) of CPU to DRAM write buffers
⎯Four cache lines of CPU to DRAM read prefetch buffers
⎯Read around write capability for
⎯Speculative DRAM read before snoop result
⎯Burst read and write operation
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⎯
⎯BIOS shadow at 16KB increment
⎯Decoupled and burst DRAM refresh with staggered RAS timing
⎯CAS before RAS or self refresh
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