BIOS Setup Utility |
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After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
3-4.1 CHIPSET FEATURES SETUP
CHIPSET FEATURES
Bank 0/1, 2/3,
4/5 DRAM
Timing
| Setting | Description | Note |
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| SDRAM | This item allows you to select the | Default |
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| 8/10ns | value in this field, depending on |
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| SDRAM | whether the board has paged |
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| 8ns | DRAMs or EDO (extended data |
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| Normal | output) DRAMs. |
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| Medium |
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| Fast |
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| Turbo |
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DRAM Clock
Host Clock | This item allows you to control the | Default |
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| DRAM speed. |
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HCLK+33M |
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SDRAM Cycle Length
2 | When synchronous DRAM is | Default |
3installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.
Bank |
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4 Bank | Increase DRAM performance. | Default | |
Interleave | Disabled |
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| 2 Bank |
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Memory Hole |
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Disabled |
| Default | |
| Enabled | Some interface cards will map their |
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| ROM address to this area. If this |
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| occurs, select [Enabled] in this field. |
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P2C/C2P Concurrency
Disabled | This item allows you to |
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Enabled | enable/disable the PCI to CPU, CPU | Default |
| to PCI concurrency |
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