SOYO SY-K7VTA manual

Motherboard Description SY-K7VTA

⎯Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank)

⎯Four cache lines (32quadwords) of CPU to DRAM write buffers

⎯Four cache lines 32 quadwords of CPU to DRAM read prefetch buffers

⎯Read around write capability for non-stalled CPU read

⎯Burst read and write operation

⎯BIOS shadow at 16KB increment

⎯Decoupled and burst DRAM refresh with staggered RAS timing

⎯CAS before RAS or self refresh

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