BIOS Setup Utility |
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After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
3-4.1 CHIPSET FEATURES SETUP
CHIPSET FEATURES
DRAM Timing By
SPD
| Setting | Description | Note |
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| Disabled | If enable the DRAM will auto |
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| Enabled | detect the DRAM timing | Default |
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DRAM Clock
SDRAM Cycle Length
100MHz | This item allows you to control the | Default |
133MHz | DRAM speed. |
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3 | When synchronous DRAM is | Default |
2installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.
Bank Interleave
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Disabled | Increase DRAM performance. | Default |
Enabled |
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Memory Hole | Disabled |
| Default |
| Enabled | Some interface cards will map |
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| their ROM address to this area. If |
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| this occurs, select [Enabled] in this |
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| field. |
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PCI master |
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Disabled | Disabled/Enabled PCI Master |
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Pipeline Req | Enabled | Pipeline Req. | Default |
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P2C/C2P Concurrency
Disabled | This item allows you to |
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Enabled | enable/disable the PCI to CPU, | Default | |
CPU to PCI concurrency. | |||
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