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DSP
SCKI
BCK
LRCK
DOUT
PCM3793A
AudioInterface
Clock
Manager
ADC
DAC
DSP
SCKI
BCK
LRCK
DOUT
PCM3793A
AudioInterface
Clock
Manager
ADC
DAC
Interfacing to DSPs
Refer to the following examples for interfacing the PCM3793A to a digital signal processor (DSP) in eitherslave or master mode. To implement master mode, MSTR = 1 of register 84 (54h) enables master modeoperation as discussed in the product data sheet . Insert 5440h to the recommended power-on sequenceafter DAC power-up (49h) of PCM3793A, as noted in Table A-2 .
Example A-1. Slave Mode Operation
Figure A-24 illustrates the proper configuration for slave mode operation.
Figure A-24. Slave Mode Operation
Example A-2. Master Mode Operation
Figure A-25 illustrates the correct interface for master mode operation.
Figure A-25. Master Mode Operation
Where:
•SCKI: Audio clock (256f
S
/ 384f
S
)
•BCK: Clock for audio transfer (32f
S
/ 48f
S
/ 64f
S
)
•LRCK: Sampling rate clock (f
S
)
•DIN: Audio data input for DAC (I
2
S, Left-Justified, Right-Justified, DSP)
•DOUT: Audio data output from ADC (I
2
S, Left-Justified, Right-Justified, DSP)
98 Reference .csv Files, Interfacing to DSPs, and Package Information SBAU127 – July 2007Submit Documentation Feedback