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Table A-2 summarizes the recommended power-on sequence for the PCM3793A. The shaded cells withinthe table indicate specific register settings that must be configured for the device to properly operate witha DSP interface.
Table A-2. Recommended Power-On Sequence for PCM3793A
REGISTERSTEP SETTINGS NOTE
1 – Turn on all power supplies.
(1)
2 4027h Headphone amplifier L-ch volume (–6dB)
(2)
3 4127h Headphone amplifier R-ch volume (–6dB)
(2)
4 4227h Speaker amplifier L-ch volume (–6dB)
(2)
5 4327h Speaker amplifier R-ch volume (–6dB)
(2)
6 4427h Digital attenuator L-ch (–24dB)
(2)
7 4527h Digital attenuator R-ch (–24dB)
(2)
8
(3)
4620h DAC audio interface format (left-justified)
(4)
9 4BC0h Headphone detection enable and inverting polarity. Short and thermal detection enable.
10
(3)
5102h ADC audio interface format (left-justified)
(4)
11 5A10h V
COM
ramp up/down time control. PG1, PG2 gain control (0dB)
12
(5)
49E0h DAC (DAL, DAR) and analog bias power up
13
(5)
5601h Zero-cross detection enable
14 4803h Analog mixer (MXL, MXR) power up
15 5811h Analog mixer input (SW2, SW5) select
16 49FCh Headphone amplifier (HPL, HPR, HPC) power up
17 4C03h Speaker amplifier shut down release
18 4A01h V
COM
power up
19 523Fh Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up
20 5711h Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
21 4F0Ch Analog input L-ch (PG3) volume (0dB)
(2)
22 500Ch Analog input R-ch (PG4) volume (0dB)
(2)
23 – Any settings for other devices or wait time, 450ms
(6) (7)
24 49FFh Speaker amplifier (SPL, SPR) power up
(5)
(1)
V
DD
should be turn on prior to or simultaneously with the other power supplies. It is recommended to set register data with thesystem clock input after turning all power supplies on.(2)
Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.(3)
I
2
S: 4620h; Left-Justified: 4601h; Right-Justified: 4602h; DSP: 4603h.(4)
Audio interface format should be set to match the DSP or decoder being used.(5)
Between steps 12 and 13, add this value for slave configuration: 5400h. For master configuration, add: 5440h.(6)
The PCM3793A requires time for V
COM
to reach the common level from GND level. The delay depends on the capacitor valuefor V
COM
and the setting of register 125 PTM[1:0], RES[4:0]. The default setting is 450ms at V
COM
= 4.7 μs.(7)
The PCM3794A does not require this setting because it has no speaker output.
Packaging information includes a thermal pad mechanical drawing and an example board layout. Theseexamples are taken from the PCM3793A product data sheet (available for download at www.ti.com ).
SBAU127 – July 2007 Reference .csv Files, Interfacing to DSPs, and Package Information 99Submit Documentation Feedback