Texas Instruments TMS320C3x 6.8 Bit-Reversed Addressing

Bit-Reversed Addressing
6-26
6.8 Bit-Reversed Addressing
The ’C3x can implement fast Fourier transforms (FFT) with bit-reversed ad-
dressing. Whenever data in increasing sequence order is transformed by an
FFT, the resulting data is presented in bit-reversed order. T o recover this data
in the correct order, certain memory locations must be swapped. By using the
bit-reversed addressing mode, swapping data is unnecessary. The data is ac-
cessed by the CPU in bit-reversed order rather than sequentially. For correct
bit-reversed access, the base address of bit-reversed access, the base ad-
dress must be located on a boundary given by the size of the FFT table. Similar
to circular addressing, the base address of bit-reversed addressing must fol-
low this criteria.
Base address must be aligned to a K-bit boundary (that is, the K LSBs of
the starting address of the buffer/table must be 0) as follows:
2
K
> R
where:
R = length of table/buffer
K = number of 0s in the LSBs of the buffer/table starting address
Size of the buffer/table must be less than or equal to 64K (16 bits)
The CPU bit-reversed operation can be illustrated by assuming an FFT table
of size 2n. When real and imaginary data are stored in separate arrays, the n
LSBs of the base address must be 0, and IR0 must be equal to 2n–1 (half of
the FFT size). When real and imaginary data are stored in consecutive
memory locations (Real0, Imaginary0, Real1, Imaginary1, Real2, Imaginary2,
etc.), the n+1 LSBs of the base address must be 0, and IR0 must be equal to
2n (FFT size).
For CPU bit-reversed addressing, one auxiliary register points to the physical
location of data. Adding IR0 (in bit-reversed addressing) to this auxiliary register
performs a reverse-carry propagation. IR0 is treated as an unsigned integer.
To illustrate bit-reversed addressing, assume 8-bit auxiliary registers. Let AR2
contain the value 0110 0000 (96). This is the base address of the data in
memory assuming a 16-entry table. Let IR0 contain the value 0000 1000 (8).
Example 6–26 shows a sequence of modifications of AR2 and the resulting
values of AR2.