Main
Page
Preface
Read This First
About This Manual
Notational Conventions
Page
Information About Cautions
Related Documentation From Texas Instruments
TMS320C3x/C4x Optimizing C Compiler Users Guide
TMS320C3x/C4x Assembly Language Tools Users Guide
TMS320C3x General Purpose Applications Users Guide
References
Digital Signal Processing with the TMS320C25.
Page
Page
Page
If You Need Assistance
x
If You Need Assistance . . .
World-Wide Web Sites
North America, South America, Central America
Europe, Middle East, Africa
Asia-Pacific
Trademarks
Contents
Description of the registers in the CPU register file.
Page
Discussion of the pipeline of operations on the TMS320C3x
Description of the boot loader operations for the C31 and C32.
Description of the DMA controller, timers, and serial ports.
List of the opcode fields for the TMS320C3x instructions.
Figures
Page
Page
Page
Page
Page
Tables
Page
Examples
Page
Page
Introduction
Chapter 1
1.1 TMS320C3x Devices
TMS320C3x Devices
1-3
Figure 11. TMS320C3x Devices Block Diagram
1.1.1 TMS320C3x Key Specifications
1.1.2 TMS320C30
1.1.3 TMS320C31 and TMS320LC31
Page
TMS320C3x Devices
1-5
Table 11. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison
TMS320C3x Devices
1-6
Table 11. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison (Continued)
Typical Applications
1.2 Typical Applications
Table 12. Typical Applications of the TMS320 Family
Architectural Overview
Chapter 2
2.1 Overview
2-3
Figure 21. TMS320C30 Block Diagram
2-4
Figure 22. TMS320C31 Block Diagram
2-5
Figure 23. TMS320C32 Block Diagram
2.2 Central Processing Unit (CPU)
Central Processing Unit (CPU)
2-7
Figure 24. Central Processing Unit (CPU)
2.2.1 Floating-Point/Integer Multiplier
Data Formats and Floating-Point Operation,
2.2.2 Arithmetic Logic Unit (ALU) and Internal Buses
Data Formats and Floating-Point Operation,
2.2.3 Auxiliary Register Arithmetic Units (ARAUs)
2.3 CPU Primary Register File
CPU Registers,
Table 21. Primary CPU Registers
Table 21. Primary CPU Registers (Continued)
Data Formats and Floating-Point Operation,
push
pop
repeat end-address register (RE)
System and User Stack Management
repeat start-address register (RS)
2.4 Other Registers
2.5 Memory Organization
2.5.1 RAM, ROM, and Cache
2-14
Figure 25. Memory Organization of the TMS320C30
2-15
Figure 26. Memory Organization of the TMS320C31
2-16
Figure 27. Memory Organization of the TMS320C32
, for more information.
Memory and the Instruction Cache
2.5.2 Memory Addressing Modes
2.6 Internal Bus Operation
2.7 External Memory Interface
External Memory Interface
2.7.1 TMS320C32 16- and 32-Bit Program Memory
2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory
Figure 28. TMS320C32-Supported Data Types and Sizes and External Memory Widths
2.8 Interrupts
Reset Operation
Status Register (ST)
2-22
2.9 Peripherals
, for more information.
Figure 29. Peripheral Modules
2.9.1 Timers
2.9.2 Serial Ports
2.10 Direct Memory Access (DMA)
DMA Controller
Figure 210. DMA Controller
Page
TMS320C30, TMS320C31, and TMS320C32 Differences
Table 22. Feature Set Comparison
CPU Registers
Chapter 3
3.1 CPU Multiport Register File
Table 31. CPU Registers
3.1.1 Extended-Precision Registers (R7R0)
Figure 31. Extended-Precision Register Floating-Point Format
Figure 32. Extended-Precision Register Integer Format
3.1.2 Auxiliary Registers (AR7AR0)
3.1.3 Data-Page Pointer (DP)
System
Circular Addressing
Direct Addressing
3.1.7 Status (ST) Register
Figure 33. Status Register (TMS320C30 andTMS320C31)
Figure 34. Status Register (TMS320C32 Only)
Table 32. Status Register Bits
Page
Table 32. Status Register Bits (Continued)
3-9
3.1.8 CPU/DMA Interrupt-Enable (IE) Register
Figure 35. CPU/DMA Interrupt-Enable (IE) Register
(TMS320C30 and TMS320C31)
Notes: 1) xx = reserved bit, read as 0 2) R = read, W = write
Table 33. IE Bits and Functions
Table 33. IE Bits and Functions(Continued)
3.1.9 CPU Interrupt Flag (IF) Register
3-12
Figure 37. TMS320C30 CPU Interrupt Flag (IF) Register
Figure 38. TMS320C31 CPU Interrupt Flag (IF) Register
Figure 39. TMS320C32 CPU Interrupt Flag (IF) Register
Table 34. IF Bits and Functions
3.1.9.1 Interrupt-Trap Table Pointer (ITTP)
Interrupts
Figure 310. Effective Base Address of the Interrupt-Trap Vector Table
3-15
Figure 311.Interrupt and Trap Vector Locations
3.1.10 I/O Flag (IOF) Register
Figure 312. I/O Flag (IOF) Register
Table 35. IOF Bits and Functions
3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers
3.2 Other Registers
Page
Memory and the Instruction Cache
Chapter 4
4.1 Memory
4.1.1 Memory Maps
4.1.1.1 TMS320C30 Memory Map
Reset/Interrupt/Trap Vector Map
4-4
Figure 41. TMS320C30 Memory Maps
4.1.1.2 TMS320C31 Memory Map
branches
Reset/Interrupt/ Trap Vector Map
4-6
Figure 42. TMS320C31 Memory Maps
4.1.1.3 TMS320C32 Memory Map
Interrupt-Trap Table Pointer (ITTP)
Reset/Interrupt/Trap Vector Map
4-8
Figure 43. TMS320C32 Memory Maps
4.1.2 Peripheral Bus Memory Map
4.1.2.1 TMS320C30 Peripheral Bus Memory Map
4-10
Figure 44. TMS320C30 Peripheral Bus Memory-Mapped Registers
4-11
4.1.2.2 TMS320C31 Peripheral Bus Memory Map
Figure 45. TMS320C31 Peripheral Bus Memory-Mapped Registers
Page
4-13
Figure 46. TMS320C32 Peripheral Bus Memory-Mapped Registers
4.2 Reset/Interrupt/Trap Vector Map
branch
Interrupt-Trap Table Pointer (ITTP)
4-15
Figure 47. Reset, Interrupt, and Trap Vector Locations for the TMS320C30 Microprocessor Mode
4-16
Figure 48. Reset, Interrupt, and Trap Vector Locations for theTMS320C31 Microprocessor Mode
Figure 49. Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode
4-18
Figure 410. Interrupt and Trap Vector Locations for TMS320C32
4.3 Instruction Cache
4.3.1 Instruction-Cache Architecture
Figure 411.Address Partitioning for Cache Control Algorithm
Figure 412. Instruction-Cache Architecture
4.3.2 Instruction-Cache Algorithm
cache miss
cache hit
align
4.3.3 Cache Control Bits
Instruction Cache
Table 41. Combined Effect of the CE and CF Bits
Example 41. Pipeline Effects of Modifying the Cache Control Bits
Data Formats and Floating-Point Operation
Chapter 5
5.1 Integer Formats
5.1.1 Short-Integer Format
si
si,
Figure 51. Short-Integer Format and Sign-Extension of Short Integers
5.2 Unsigned-Integer Formats
5.2.1 Short Unsigned-Integer Format
si
Figure 53. Short Unsigned-Integer Format and Zero Fill
5.2.2 Single-Precision Unsigned-Integer Format
5.3 Floating-Point Formats
Figure 55. General Floating-Point Format
5.3.1 Short Floating-Point Format
Figure 56. Short Floating-Point Format
5.3.2 TMS320C32 Short Floating-Point Format for External 16-Bit Data
Figure 57. TMS320C32 Short Floating-Point Format for External 16-Bit Data
5.3.3 Single-Precision Floating-Point Format
Figure 58. Single-Precision Floating-Point Format
5.3.4 Extended-Precision Floating-Point Format
Figure 59. Extended-Precision Floating-Point Format
5.3.5 Determining the Decimal Equivalent of a TMS320C3x Floating-Point Format
Example 51. Positive Number
Floating-Point Formats
Example 52. Negative Number
Example 53. Fractional Number
5.3.6 Conversion Between Floating-Point Formats
x
y
s
Figure 510. Converting from Short Floating-Point Format to Single-Precision Floating-Point Format
The 8 LSBs of the mantissa field are filled with 0s.
The 8 LSBs of the mantissa field are truncated.
5.4 Floating-Point Conversion (IEEE Std. 754)
Figure 514. IEEE Single-Precision Std. 754 Floating-Point Format
Figure 515. TMS320C3x Single-Precision 2s-Complement Floating-Point Format
ss.f
s
5.4.1 Converting IEEE Format to 2s-Complement TMS320C3x Floating-Point Format
Table 51. Converting IEEE Format to 2s-Complement Floating-Point Format
Page
5.4.1.1 IEEE-to-TMS320C3x Floating-Point Format Conversion
Example 54. IEEE-to-TMS320C3x Conversion (Fast Version)
Example 54.IEEE-to-TMS320C3x Conversion (Fast Version) (Continued)
Example 55. IEEE-to-TMS320C3x Conversion (Complete Version)
5-20
Example 55.IEEE-to-TMS320C3x Conversion (Complete Version) (Continued)
NEG POPF R0 ; Load this as a flt. pt. number NEGF R0,R0 ; Negate if original sign negative RETS
5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format to IEEE Format
Table 52. Converting 2s-Complement Floating-Point Format to IEEE Format
5.4.2.1 TMS320C3x-to-IEEE Floating-Point Format Conversion
Example 56. TMS320C3x-to-IEEE Conversion (Fast Version)
Example 56.TMS320C3x-to-IEEE Conversion (Fast Version) (Continued)
Example 57. TMS320C3x-to-IEEE Conversion (Complete Version)
Example 57.TMS320C3x-to-IEEE Conversion (Complete Version) (Continued)
5.5 Floating-Point Multiplication
Page
5-28
Figure 516. Flowchart for Floating-Point Multiplication
Example 58. Floating-Point Multiply (Both Mantissas = 2.0)
5-30
Example 59. Floating-Point Multiply (Both Mantissas = 1.5)
0001.0000000000000000000000000000000000000000000000 y 2
01.00000000000000000000000 2(
= 1.0 2
and
Example 511. Floating-Point Multiply Between Positive and Negative Numbers
(
= 128).
exp
= 0,
5.6 Floating-Point Addition and Subtraction
Floating-Point Addition and Subtraction
5-33
Figure 517. Flowchart for Floating-Point Addition
Example 513. Floating-Point Addition
Example 514. Floating-Point Subtraction
Example 515. Floating-Point Addition With a 32-Bit Shift
Page
5.7 Normalization Using the NORM Instruction
Example 517. NORM Instruction
Normalization Using the NORM Instruction
5-38
Figure 518. Flowchart for NORM Instruction Operation
5.8 Rounding (RND Instruction)
c
Rounding (RND Instruction)
5-40
Figure 519. Flowchart for Floating-Point Rounding by the RND Instruction
5.9 Floating-Point to Integer Conversion (FIX Instruction)
Floating-Point to Integer Conversion (FIX Instruction)
5-42
Figure 520. Flowchart for Floating-Point to Integer Conversion by FIX Instruction
Integer to Floating-Point Conversion (FLOAT Instruction)
5-43
5.10 Integer to Floating-Point Conversion (FLOAT Instruction)
Figure 521. Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction
5.11 Fast Logarithms on a Floating-Point Device
5.11.1 Example of Fast Logarithm on a Floating-Point Device
Table 53. Squaring Operation of F0 = 1.5
Figure 522. Tabulated Values for Mantissa
ln
5.11.2 Points to Consider
Fast Logarithms on a Floating-Point Device
Figure 523. Fast Logarithm for FFT Displays
Addressing Modes
Chapter 6
6.1 Addressing Types
Register Addressing
Addressing Modes
6.2 Register Addressing
In register addressing, a CPU register contains the operand, as shown in this example:
Table 61. CPU Register Address/Assembler Syntax and Function
6.3 Direct Addressing
Figure 61. Direct Addressing
Example 61. Direct Addressing
6.4 Indirect Addressing
Example 62. Auxiliary Register Indirect
Figure 62. Indirect Addressing Operand Encoding
Table 62. Indirect Addressing
Table 62. Indirect Addressing (Continued)
Example 63 through Example 619 show the operation for each type of indirect addressing.
Example 63. Indirect Addressing With Predisplacement Add
Example 64. Indirect Addressing With Predisplacement Subtract
Example 65. Indirect Addressing With Predisplacement Add and Modify
Example 66. Indirect Addressing With Predisplacement Subtract and Modify
Example 67. Indirect Addressing With Postdisplacement Add and Modify
Example 68. Indirect Addressing With Postdisplacement Subtract and Modify
Example 69. Indirect Addressing With Postdisplacement Add and Circular Modify
Example 610. Indirect Addressing With Postdisplacement Subtract and Circular Modify
Example 611. Indirect Addressing With Preindex Add
Example 612. Indirect Addressing With Preindex Subtract
Example 613. Indirect Addressing With Preindex Add and Modify
Example 614. Indirect Addressing With Preindex Subtract and Modify
Example 615. Indirect Addressing With Postindex Add and Modify
Example 616. Indirect Addressing With Postindex Subtract and Modify
Example 617. Indirect Addressing With Postindex Add and Circular Modify
Example 618. Indirect Addressing With Postindex Subtract and Circular Modify
Example 619. Indirect Addressing With Postindex Add and Bit-Reversed Modify
6.5 Immediate Addressing
Example 620. Short-Immediate Addressing
Example 621. Long-Immediate Addressing
6.6 PC-Relative Addressing
Example 622. PC-Relative Addressing
Figure 63. Encoding for 24-Bit PC-Relative Addressing Mode
6.7 Circular Addressing
Figure 64. Logical and Physical Representation of Circular Buffer
Figure 65. Logical and Physical Representation of Circular Buffer after Writing Three Values
Figure 66. Logical and Physical Representation of Circular Buffer after Writing Eight Values
R
Example 623. Examples of Formula
K
index
Figure 67. Circular Buffer Implementation
Example 624. Circular Addressing
Figure 68. Data Structure for FIR Filters
Circular Addressing
Addressing Modes
Example 625. FIR Filter Code Using Circular Addressing
6.8 Bit-Reversed Addressing
R
K
Example 626. Bit-Reversed Addressing
Table 63. Index Steps and Bit-Reversed Addressing
6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools
6.10 System and User Stack Management
6.10.1 System-Stack Pointer
Figure 69. System Stack Configuration
6.10.2 Stacks
Figure 610. Implementations of High-to-Low Memory Stacks
Figure 611.Implementations of Low-to-High Memory Stacks
6.10.3 Queues
Program Flow Control
Chapter 7
7.1 Repeat Modes
Table 71. Repeat-Mode Registers
7.1.1 Repeat-Mode Control Bits
7.1.2 Repeat-Mode Operation
Example 71. Repeat-Mode Control Algorithm
7.1.3 RPTB Instruction
Example 72. RPTB Operation
7.1.4 RPTS Instruction
(src
7.1.5 Repeat-Mode Restrictions
Example 73. Incorrectly Placed Standard Branch
Example 74. Incorrectly Placed Delayed Branch
7.1.6 RC Register Value After Repeat Mode Completes
Example 75. Pipeline Conflict in an RPTB Instruction
7.1.7 Nested Block Repeats
7.2 Delayed Branches
Delayed Branches
Example 76. Incorrectly Placed Delayed Branches
Example 77. Delayed Branch Execution
7.3 Calls, Traps, and Returns
Figure 71. CALL Response Timing
7.4 Interlocked Operations
Table 72. Interlocked Operations
External Memory Interface,
Page
7.4.1 Interrupting Interlocked Operations
7.4.2 Using Interlocked Operations
Pipeline Effects of Interlocked Instructions
Example 78. Busy-Waiting Loop
Example 79. Multiprocessor Counter Manipulation
Figure 72. Multiple TMS320C3xs Sharing Global Memory
Example 710. Implementation of V(S)
Example 711. Implementation of P(S)
Figure 73. Zero-Logic Interconnect of TMS320C3x Devices
Example 712. Code to Synchronize Two TMS320C3x Devices at the Software Level
7.4.3 Pipeline Effects of Interlocked Instructions
I/O Flag Register (IOF)
Interlocked Operations
Example 713. Pipeline Delay of XF Pin Configuration
Example 714. Incorrect Use of Interlocked Instructions
7.5 Reset Operation
Table 73. TMS320C3x Pin Operation at Reset
Page
Page
Page
C30 and C31 External-Memory Interface
7.6 Interrupts
DMA and Interru pts
Serial-Port Interrupt Sources
Timer Inter- rupts
7.6.1 TMS320C30 and TMS320C31 Interrupt Vector Table
Page
Table 75. Reset, Interrupt, and Trap-Branch Locations for the TMS320C31 Microcomputer Boot Mode
7.6.2 TMS320C32 Interrupt Vector Table
Figure 74.Effective Base Address of the Interrupt-Trap-Vector Table
Table 76. Interrupt and Trap-Vector Locations for the TMS320C32
7.6.3 Interrupt Prioritization
Table 77. Reset and Interrupt Vector Priorities
7.6.4 CPU Interrupt Control Bits
7.6.5 Interrupt Flag Register Behavior
Figure 75. IF Register Modification
7.6.6 Interrupt Processing
Figure 76. CPU Interrupt Processing
7.6.7 CPU Interrupt Latency
Table 78. Interrupt Latency
7.6.8 External Interrupts
CPU Interrupt Flag (IF) Register
Figure 77. Interrupt Logic Functional Diagram
7.7 DMA Interrupts
7.7.1 DMA Interrupt Control Bits
CPU/DMA Interrupt-Enable Register (IE)
DMA Registers
7.7.2 DMA Interrupt Processing
Figure 78.DMA Interrupt Processing
DMA Interrupts
7.7.3 CPU/DMA Interaction
Figure 79. Parallel CPU and DMA Interrupt Processing
7.7.4 TMS320C3x Interrupt Considerations
decode
read
Table 79. Pipeline Operation with PUSH ST
Table 710. Pipeline Operation with Load Followed by Interrupt
Example 715. Pending Interrupt
7.7.5 TMS320C30 Interrupt Considerations
false
true,
Page
Page
7.8 Traps
7.8.1 Initialization of Traps and Interrupts
7.8.2 Operation of Traps
Figure 710. Flow of Traps
Page
7.9 Power Management Modes
7.9.1 IDLE2 Power-Down Mode
Figure 711.IDLE2 Timing
Power Management Modes
Figure 712. Interrupt Response Timing After IDLE2 Operation
7.9.2 LOPOWER
Power Management Modes
Figure 713. LOPOWER Timing
Figure 714. MAXSPEED Timing
Pipeline Operation
Chapter 8
8.1 Pipeline Structure
Figure 81. TMS320C3x Pipeline Structure
Page
8.2 Pipeline Conflicts
nop
8.2.1 Branch Conflicts
Example 81. Standard Branch
Example 82. Delayed Branch
8.2.2 Register Conflicts
Example 83. Write to an AR Followed by an AR for Address Generation
Example 84. A Read of ARs Followed by ARs for Address Generation
8.2.3 Memory Conflicts
Memory Access for Maximum Performance
8.2.3.1 Program Wait
Example 85. Program Wait Until CPU Data Access Completes
Example 86. Program Wait Due to Multicycle Access
8.2.3.2 Program Fetch Incomplete
Example 87. Multicycle Program Memory Fetches
8.2.3.3 Execute Only
Pipeline Conflicts
Example 88. Single Store Followed by Two Reads
STFR 0,*AR1 ; R0 *AR1 LDF *AR2,R1 ; *AR2 R1 in parallel with
LDF *AR3,R2 ; *AR3
Example 89. Parallel Store Followed by Single Read
Example 810. Interlocked Load
8.2.3.4 Hold Everything
Pipeline Conflicts
Example 811. Busy External Port
STF R0,@DMA1 LDF @DMA2,R0
Example 812. Multicycle Data Reads
Example 813. Conditional Calls and Traps
8.3 Resolving Register Conflicts
Example 814. Address Generation Update of an AR Followed by an AR for Address Generation
Example 815. Write to an AR Followed by an AR for Address Generation Without a Pipeline Conflict
Example 816. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict
8.4 Memory Access for Maximum Performance
Table 81. One Program Fetch and One Data Access for Maximum Performance
Memory Access for Maximum Performance
Table 82. One Program Fetch and Two Data Accesses for Maximum Performance
8.5 Clocking Memory Accesses
Figure 82. Minor Clock Periods
8.5.1 Program Fetches
8.5.2 Data Loads and Stores
8.5.2.1 2-Operand Instruction Memory Accesses
Figure 83. 2-Operand Instruction Word
8.5.2.2 3-Operand Instruction Memory Reads
Figure 84. 3-Operand Instruction Word
Page
Clocking Memory Accesses
Example 817. Dummy sr2 Read
STI R0,*AR6 ; AR6 points to MSTRB space ADDI3 *AR1,*AR3,R0 ; AR3 points to on-chip RAM (
1) ; AR1 points to MSTRB space (
2)
Clocking Memory Accesses
Example 818. Operand Swapping Alternative
Switch the operands of the 3-operand instruction so that the internal read is performed first.
STI R0,*AR6 ; AR6 points to MSTRB space ADDI3 *AR3,*AR1,R0 ; AR3 points to on-chip RAM (
2) ; AR1 points to MSTRB space (
1)
Figure 85. Multiply or CPU Operation With a Parallel Store
Figure 86. Two Parallel Stores
Figure 87. Parallel Multiplies and Adds
TMS320C30 and TMS320C31 External-Memory Interface
Chapter 9
Enhanced External-Memory Interface
9.1 Overview
9.2 Memory Interface Signals
9.2.1 TMS320C30 Memory Interface Signals
9.2.2 TMS320C31 Memory Interface Signals
Table 91. Primary Bus Interface Signals
Table 92. Expansion Bus Interface Signals
9-6
Figure 91. Memory-Mapped External Interface Control Registers
9.3 Memory Interface Control Registers
9.3.1 Primary-Bus Control Register
Figure 92. Primary-Bus Control Register
Memory Interface Control Registers
Table 93. Primary-Bus Control Register Bits
9.3.2 Expansion-Bus Control Register
Figure 93. Expansion-Bus Control Register
Table 94. Expansion-Bus Control Register Bits
9.4 Programmable Wait States
Programmable Wait States
Table 95. Wait-State Generation
9.5 Programmable Bank Switching
Figure 94. BNKCMP Example
Table 96. BNKCMP and Bank Size
Page
Figure 95. Bank-Switching Example
9.6 External Memory Interface Timing
9.6.1 Primary-Bus Cycles
Page
9-17
Figure 96. Read-Read-Write for (M)STRB = 0
Note: Back-to-Back Read Operations (M)STRB remains low during back-to-back read operations.
Figure 97. Write-Write-Read for (M)STRB = 0
Figure 98. Use of Wait States for Read for (M)STRB = 0
Figure 99. Use of Wait States for Write for (M)STRB = 0
9.6.2 Expansion-Bus I/O Cycles
Figure 910. Read and Write for IOSTRB = 0
Figure 911.Read With One Wait State for IOSTRB = 0
Figure 912. Write With One Wait State for IOSTRB = 0
9-24
Figure 913. Memory Read and I/O Write for Expansion Bus
9-25
Figure 914. Memory Read and I/O Read for Expansion Bus
Figure 915. Memory Write and I/O Write for Expansion Bus
Figure 916. Memory Write and I/O Read for Expansion Bus
Figure 917. I/O Write and Memory Write for Expansion Bus
Figure 918. I/O Write and Memory Read for Expansion Bus
9-30
Figure 919. I/O Read and Memory Write for Expansion Bus
Figure 920. I/O Read and Memory Read for Expansion Bus
9-32
Figure 921. I/O Write and I/O Read for Expansion Bus
Figure 922. I/O Write and I/O Write for Expansion Bus
Figure 923. I/O Read and I/O Read for Expansion Bus
Figure 924. Inactive Bus States for IOSTRB
Figure 925. Inactive Bus States for STRB and MSTRB
9.6.3 Hold Cycles
Figure 926. HOLD and HOLDA Timing
TMS320C32 Enhanced External Memory Interface
Chapter 10
10.1 TMS320C32 Memory Features
10.2 TMS320C32 Memory Overview
10.2.1 External Memory Interface Overview
Figure 101. Memory Address Spaces
10.2.2 Program Memory Access
Figure 102. Status Register
10.2.3 Data Memory Access
10.2.3.1 8-, 16-, or 32-Bit Integers Data Types
Page
10.3 Configuration
10.3.1 External Interface Control Registers
Figure 103. Memory-Mapped External Interface Control Registers
10.3.1.1 STRB0 Control Register
Figure 104. STRB0 Control Register
10.3.1.2 STRB1 Control Register
Figure 105. STRB1 Control Register
10.3.1.3 IOSTRB Control Register
Figure 106. IOSTRB Control Register
Table 101 describes the bits in the STRBO, STRB1, and the IOSTRB control registers.
Table 101. STRB0, STRB1, and IOSTRB Control Register Bits
Configuration
Table 101. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)
Configuration
Figure 107. STRB Configuration
10.3.2 Using Physical Memory Width and Data-Type Size Fields
Table 102. Data-Access Sequence for a Memory Configuration with Two Banks
10.4 Programmable Wait States
Programmable Wait States
Table 103. Wait-State Generation
10.5 Programmable Bank Switching
Figure 108. BNKCMP Example
Table 104. BNKCMP and Bank Size
Figure 109. Bank-Switching Example
Page
10.6 32-Bit-Wide Memory Interface
Figure 1010. TMS320C32 External Memory Interface for 32-Bit SRAMs
Case 1: 32-Bit-Wide Memory With 8-Bit Data-Type Size
10-21
Table 105. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Type Size
A
Active Strobe Byte Enable 0 0 STRBx_B0 0 1 STRBx_B1 1 0 STRBx_B2 1 1 STRBx_B3
Figure 1011. Functional Diagram for 8-Bit Data-Type Size and 32-Bit External-Memory
Table 106. Example of 8-Bit Data-Type Size
Case 2: 32-Bit-Wide Memory With 16-Bit Data-Type Size
Table 107. Strobe Byte-Enable for 32-Bit-Wide Memory With 16-Bit Data-Type Size
10-23
Figure 1012. Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory Width
Address Pins Active Strobe Byte Enable Accessed
Address Bus External
Table 108. Example of 16-Bit Data-Type Size and 32-Bit-Wide External Memory
10-24
Case 3: 32-Bit-Wide Memory With 32-Bit Data-Type Size
Figure 1013. Functional Diagram for 32-Bit Data Size and 32-Bit External-Memory Width
Table 109. Example of 32-Bit-Wide Memory With 32-Bit Data-Type Size
10.7 16-Bit-Wide Memory Interface
Figure 1014. External-Memory Interface for 16-Bit SRAMs
Case 4: 16-Bit-Wide Memory With 8-Bit Data-Type Size
Table 1010. Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size
Figure 1015. Functional Diagram for 8-Bit Data-Type Size and 16-Bit External-Memory Width
the pins listed in Table 1011.
Table 1011. Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory
Case 5: 16-Bit-Wide Memory With 16-Bit Data-Type Size
Figure 1016. Functional Diagram for 16-Bit Data-Type Size and 16-Bit External-Memory
the pins listed in Table 1012.
Table 1012. Example of 16-Bit-Wide Memory With 16-Bit Data-Type Size
Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type Size
the pins listed in Table 1013.
Figure 1017. Functional Diagram for 32-Bit Data-Type Size and 16-Bit External-Memory
Table 1013. Example of 16-Bit-Wide Memory With 32-Bit Data-Type Size
10.8 8-Bit-Wide Memory Interface
Figure 1018. External Memory Interface for 8-Bit SRAMs
Case 7: 8-Bit-Wide Memory With 8-Bit Data-Type Size
Figure 1019. Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory
Table 1014. Example of 8-Bit-Wide Memory With 8-Bit Data-Type Size
Case 8: 8-Bit Wide Memory With 16-Bit Data-Type Size
Figure 1020. Functional Diagram for 16-Bit Data-Type Size and 8-Bit External-Memory
Table 1015. Example of 8-Bit-Wide Memory With 16-Bit Data-Type Size
Case 9: 8-Bit-Wide Memory With 32-Bit Data-Type Size
Figure 1021. Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-Memory
Table 1016. Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory
10.9 External Ready Timing Improvement
Figure 1022. RDY Timing for Memory Read
10.10 Bus Timing
TMS320C32 Data Sheet
10.10.1 STRB0 and STRB1 Bus Cycles
10-40
Figure 1023. Read-Read-Write Sequence for STRBx Active
Figure 1024. Write-Write-Read Sequence for STRBx Active
Figure 1025. One Wait-State Read Sequence for STRBx Active
Figure 1026. One Wait-State Write Sequence for STRBx Active
10.10.2 IOSTRB Bus Cycles
Figure 1027. Zero Wait-State Read and Write Sequence for IOSTRB Active
10-44
Figure 1028. One Wait-State Read Sequence for IOSTRB Active
Figure 1029. One Wait-State Write Sequence for IOSTRB Active
10-45
Figure 1030. STRBx Read and IOSTRB Write
Figure 1031. STRBx Read and IOSTRB Read
10-46
Figure 1032. STRBx Write and IOSTRB Write
Figure 1033. STRBx Write and IOSTRB Read
Figure 1034. IOSTRB Write and STRBx Write
10-48
Figure 1035. IOSTRB Write and STRBx Read
Figure 1036. IOSTRB Read and STRBx Write
10-49
Figure 1037. IOSTRB Read and STRBx Read
Figure 1038 through Figure 1040 illustrate the transitions between reads and writes.
10-50
Figure 1038. IOSTRB Write and Read
Figure 1039. IOSTRB Write and Write
10-51
Figure 1040. IOSTRB Read and Read
10.10.3 Inactive Bus States
Figure 1041. Inactive Bus States Following IOSTRB Bus Cycle
Figure 1042. Inactive Bus States Following STRBx Bus Cycle
Page
11.1 TMS320C31 Boot Loader
11.1.1 TMS320C31 Boot-Loader Description
Serial Ports
11.1.2 TMS320C31 Boot-Loader Mode Selection
11-3
Table 111. Boot-Loader Mode Selection
Figure 111.TMS320C31 Boot-Loader Mode-Selection Flowchart
11.1.3 TMS320C31 Boot-Loading Sequence
11-5
Figure 112.Boot-Loader Memory-Load Flowchart
11-6
Figure 113.Boot-Loader Serial-Port Load-Mode Flowchart
11.1.4 TMS320C31 Boot Data Stream Structure
Table 112. Source Data Stream Structure
j
11.1.4.1 Examples of External TMS320C31 Memory Loads
Table 113. Byte-Wide Configured Memory
Table 114. 16-Bit-Wide Configured Memory
Table 115. 32-Bit-Wide Configured Memory
11.1.4.2 Serial-Port Loading
11.1.5 Interrupt and Trap-Vector Mapping
Table 116. TMS320C31 Interrupt and Trap Memory Maps
11.1.6 TMS320C31 Boot-Loader Precautions
11.2 TMS320C32 Boot Loader
11.2.1 TMS320C32 Boot-Loader Description
11.2.2 TMS320C32 Boot-Loader Mode Selection
Table 117. Boot-Loader Mode Selection
11.2.3 TMS320C32 Boot-Loading Sequence
Page
11-17
Figure 114.TMS320C32 Boot-Loader Mode-Selection Flowchart
Figure 115.Boot-Loader Serial-Port Load Flowchart
Figure 116.Boot-Loader Memory-Load Flowchart
Figure 117.Handshake Data-Transfer Operation
11.2.4 TMS320C32 Boot Data Stream Structure
Table 118. Source Data Stream Structure
x
Table 118. Source Data Stream Structure (Continued)
11.2.5 Boot-Loader Hardware Interface
Figure 118. External Memory Interface for Source Data Stream Memory Boot Load
11.2.6 TMS320C32 Boot-Loader Precautions
Page
Peripherals
Chapter 12
12.1 Timers
Figure 121. Timer Block Diagram
12.1.1 Timer Pins
12.1.2 Timer Control Registers
Figure 122. Memory-Mapped Timer Locations
12.1.3 Timer Global-Control Register
Figure 123. Timer Global-Control Register
Table 121. Timer Global-Control Register Bits Summary
Timer Operation Modes
Table 121. Timer Global-Control Register Bits Summary (Continued)
Timer Operation Modes
12.1.4 Timer-Period and Counter Registers
12.1.5 Timer Pulse Generation
Figure 124. Timer Timing
f(pulse mode)
f(timer clock) / (
f(timer clock) / period register f(clock mode)
period register)
Example 121. Timer Output Generation Examples
12.1.6 Timer Operation Modes
12.1.6.1 CLKSRC = 1 and FUNC = 0
Figure 125. Timer Configuration with CLKSRC = 1 and FUNC = 0
12.1.6.2 CLKSRC = 1 and FUNC = 1
Figure 126. Timer Configuration with CLKSRC = 1 and FUNC = 1
12.1.6.3 CLKSRC = 0 and FUNC = 0
Figure 127. Timer Configuration with CLKSRC = 0 and FUNC = 0
12.1.6.4 CLKSRC = 0 and FUNC = 1
Figure 128. Timer Configuration with CLKSRC = 0 and FUNC = 1
12.1.7 Using TCLKx as General-Purpose I/O Pins
Figure 129. TCLK as an Input (I/O = 0)
Figure 1210. TCLK as an Output (I/O = 1)
12.1.8 Timer Interrupts
12.1.9 Timer Initialization/Reconfiguration
Example 122. Maximum Frequency Timer Clock Setup
12.2 Serial Ports
12-16
Figure 1211. Serial Port Block Diagram
Figure 1212. Memory-Mapped Locations for the Serial Ports
12.2.1 Serial-Port Global-Control Register
Figure 1213. Serial-Port Global-Control Register
Table 122. Serial-Port Global-Control Register Bits Summary
Page
Page
Page
12.2.2 FSX/DX/CLKX Port-Control Register
Figure 1214. FSX/DX/CLKX Port-Control Register
Table 123. FSX/DX/CLKX Port-Control Register Bits Summary
Table 123. FSX/DX/CLKX Port-Control Register Bits Summary (Continued)
12.2.3 FSR/DR/CLKR Port-Control Register
Figure 1215. FSR/DR/CLKR Port-Control Register
Table 124. FSR/DR/CLKR Port-Control Register Bits Summary
12.2.4 Receive/Transmit Timer-Control Register
Figure 1216. Receive/Transmit Timer-Control Register
Table 125. Receive/Transmit Timer-Control Register Register Bits Summary
Page
Table 125. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)
12.2.5 Receive/Transmit Timer-Counter Register
It is also set to 0 at reset.
Figure 1217. Receive/Transmit Timer-Counter Register
12.2.6 Receive/Transmit Timer-Period Register
cleared to 0 at reset
Figure 1218. Receive/Transmit Timer-Period Register
12.2.7 Data-Transmit Register
Figure 1219. Transmit Buffer Shift Operation
Figure 1220. Receive Buffer Shift Operation
12.2.9 Serial-Port Operation Configurations
12-30
Figure 1221. Serial-Port Clocking in I/O Mode
Figure 1222. Serial-Port Clocking in Serial-Port Mode
12.2.10 Serial-Port Timing
Page
12.2.10.1 Continuous Transmit and Receive Modes
12.2.10.2 Handshake Mode
Figure 1223. Data Word Format in Handshake Mode
Figure 1224. Single 0 Sent as an Acknowledge Bit
Figure 1225. Direct Connection Using Handshake Mode
12.2.11 Serial-Port Interrupt Sources
12.2.12 Serial-Port Functional Operation
12.2.12.1 Fixed Data-Rate Timing Operation
Figure 1226. Fixed Burst Mode
Figure 1227. Fixed Standard Mode With Back-to-Back Frame Sync
Figure 1228. Fixed Continuous Mode Without Frame Sync
Figure 1229. Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal
12.2.12.2 Variable Data-Rate Timing Operation
Figure 1230. Variable Burst Mode
Serial-Port Functional Operation
Figure 1231. Variable Standard Mode With Back-to-Back Frame Syncs
N
Figure 1232. Variable Continuous Mode Without Frame Sync
12.2.13 Serial-Port Initialization/Reconfiguration
12.2.14 TMS320C3x Serial-Port Interface Examples
12.2.14.1 Handshake Mode Example
Example 123. Serial-Port Register Setup #1
Timers
Example 124. Serial-Port Register Setup #1
Example 125. Serial-Port Register Setup #2
12.2.14.2 CPU Transfer With Serial Port Transmit Polling Method
Example 126. CPU Transfer With Serial Port Transmit Polling Method
12.2.14.3 DMA Transfer With Serial Port Interrupt
12.2.14.4 Serial Analog Interface Chips Interface Example
Figure 1233. TMS320C3x Zero-Glue-Logic Interface to TLC320C4x Example
12.2.14.5 Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface Example
Example 127. TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A
Page
12.3 DMA Controller
12.3.1 DMA Functional Description
12.3.1.1 TMS320C30 and TMS320C31 DMA Controller
12.3.1.2 TMS320C32 Two-Channel DMA Controller
12.3.2 DMA Basic Operation
and
Figure 1234. DMA Basic Operation
12.3.3 DMA Registers
Figure 1235. Memory-Mapped Locations for DMA Channels
12-53
12.3.3.1 DMA Global-Control Register
Figure 1236. TMS320C30 and TMS320C31 DMA Global-Control Register
Figure 1237. TMS320C32 DMA0 Global-Control Register
Figure 1238. TMS320C32 DMA1 Global-Control Register
Table 126. DMA Global-Control Register Bits Summary
Page
Table 126. DMA Global-Control Register Bits Summary (Continued)
12.3.3.2 Destination-Address and Source-Address Registers
Figure 1239. DMA Controller Address Generation
12.3.3.3 Transfer-Counter Register
Figure 1240. Transfer-Counter Operation
12.3.4 CPU/DMA Interrupt-Enable Register
12-60
Figure 1241. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register
xx EDINT ETINT1 ETINT0 ERINT1 EXINT1
Notes: 1) R = read, W = write 2) xx = reserved bit, read as 0
Figure 1242. TMS320C32 CPU/DMA Interrupt-Enable Register
Notes: 1) R = read, W = write 2) xx = reserved bit, read as 0
Table 127. CPU/DMA Interrupt-Enable Register Bits
Table 127. CPU/DMA Interrupt-Enable Register Bits (Continued)
12.3.5 TMS320C32 DMA Internal Priority Schemes
12.3.5.1 Fixed Priority Scheme
12.3.5.2 Rotating Priority Scheme
12.3.6 CPU and DMA Controller Arbitration
Clocking Memory Access,
Table 128.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules
12.3.7 DMA and Interrupts
Interrupt Vector Table and Prioritization
12.3.7.1 Interrupts and Synchronization of DMA Channels
Figure 1243. Mechanism for No DMA Synchronization
Figure 1244. Mechanism for DMA Source Synchronization
Figure 1245. Mechanism for DMA Destination Synchronization
Figure 1246. Mechanism for DMA Source and Destination Synchronization
12.3.8 DMA Memory Transfer Timing
12.3.8.1 Single DMA Memory Transfer Timing
T
12-69
Figure 1247. DMA Timing When Destination is On Chip
C
12-70
Figure 1248. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus
12-71
Figure 1248. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)
Write followed by read incurs in one extra half-cycle.
12-72
Figure 1249. DMA Timing When Destination is an IOSTRB Bus
Write followed by read incurs in one extra cycle.
12.3.9 DMA Initialization/Reconfiguration
12.3.10 Hints for DMA Programming
12.3.11 DMA Programming Examples
.text
.bss
.data
.text
Example 128. Array Initialization With DMA
12-76
Example 129. DMA Transfer With Serial-Port Receive Interrupt
Example 1210. DMA Transfer With Serial-Port Transmit Interrupt
Example 1210. DMA Transfer With Serial-Port Transmit Interrupt (Continued)
Page
Assembly Language Instructions
Chapter 13
Optional Assembler Syntax
13.1 Instruction Set
13.1.1 Load and Store Instructions
Table 131. Load and Store Instructions
Instruction Set
13.1.2 2-Operand Instructions
Table 132. 2-Operand Instructions
13.1.3 3-Operand Instructions
Table 133. 3-Operand Instructions
13.1.4 Program-Control Instructions
Table 134. Program-Control Instructions
13.1.5 Low-Power Control Instructions
Table 135. Low-Power Control Instructions
13.1.6 Interlocked-Operations Instructions
Table 136. Interlocked-Operations Instructions
13.1.7 Parallel-Operations Instructions
Table 137. Parallel Instructions
Instruction Set
Table 137. Parallel Instructions (Continued)
(a) Parallel arithmetic with store instructions (Continued)
Table 137. Parallel Instructions (Continued)
13.1.8 Illegal Instructions
13.2 Instruction Set Summary
Table 138. Instruction Set Summary
Page
Page
Page
Instruction Set Summary
Instruction Set Summary
Page
13.3 Parallel Instruction Set Summary
Table 139. Parallel Instruction Set Summary
Page
Table 139. Parallel Instruction Set Summary (Continued)
13.4 Group Addressing Mode Instruction Encoding
13.4.1
Figure 131 shows the encoding for the general addressing modes. The notation mod
indicates the modification field that goes with the AR
field. Refer to Table 1310 on page 13-22 for further information.
Figure 131. Encoding for General Addressing Modes
Table 1310. Indirect Addressing
Table 1310. Indirect Addressing (Continued)
13.4.2 3-Operand Addressing Modes
operation
3
modm
modn
Figure 132. Encoding for 3-Operand Addressing Modes
13.4.3 Parallel Addressing Modes
Figure 133. Encoding for Parallel Addressing Modes
Figure 134. Encoding for Extended Parallel Addressing Instructions
13.4.4 Conditional-Branch Addressing Modes
Figure 135. Encoding for Conditional-Branch Addressing Modes
(c) CALL
(b) B
(a) DB
13.5 Condition Codes and Flags
Table 1311. Output Value Formats
Individual Instruction Descriptions,
Figure 136. Status Register
Condition Codes and Flags
Table 1312. Condition Codes and Flags
(a) Unconditional compares
(b) Unsigned compares
C AND Z
(c) Signed compares
Table 1312. Condition Codes and Flags (Continued)
(d) Compare to zero
N AND
(e) Compare to condition flags
13.6 Individual Instructions
Software Applications
TMS320C3x General- Purpose Applications Users Guide
13.6.1 Symbols and Abbreviations
Table 1313. Instruction Symbols
13.6.2 Optional Assembler Syntax
is equivalent to
label assembles to next source line
is not legal.
or
Individual Instructions
Use the syntax in Table 1314 to designate CPU registers in operands. Note the alternate notation R
Table 1314. CPU Register Syntax
Page
Page
Page
Page
ABSF
Page
ABSF||STF
Page
ABSI
Page
ABSI||STI
ADDC
Page
ADDC3
Add Integer With Carry, 3-Operand
See Section 8.5.2,
13-50
Page
ADDF
Add Floating-Point Values
13-52
Example ADDF *AR4++(IR1),R5
Page
ADDF3
Add Floating Point, 3-Operand
See Section 8.5.2,
13-54
Page
ADDF3||STF
ADDI
ADDI3
Add Integer, 3-Operand
ADDl3
13-59
Assembly Language Instructions
Example 1 ADDI3 R4,R7,R5
See Section 8.5.2,
ADDI3||STI
ADDl3||STI
AND
Page
AND3
Bitwise-Logical AND, 3-Operand
See Section 8.5.2,
13-64
Page
AND3||STI
Page
ANDN
Bitwise-Logical AND With Complement
13-68
Example ANDN @980Ch,R2
Page
ANDN3
Bitwise-Logical ANDN, 3-Operand
See Section 8.5.2,
13-70
Page
ASH
Page
Page
Page
Page
Page
Page
Page
Bcond
Page
BcondD
BR
src
Pipeline Con- flicts
BRD
CALL
CALLcond
Call Subroutine Conditionally
CALLcond
13-87
Assembly Language Instructions
Example CALLNZ R5
CMPF
Compare Floating-Point Value
CMPF
13-89
Assembly Language Instructions
Example CMPF *+AR4,R6
Page
CMPF3
CMPI
src, dst
dst
src
dst
Page
CMPI3
Page
DBcond
Page
DBcondD
Page
FIX
Floating-Point-to-Integer Conversion
13-100
Example FIX R1,R2
Page
FIX||STI
Page
FLOAT
Integer-to-Floating-Point Conversion
13-104
Example FLOAT *++AR2(2),R5
Page
FLOAT||STF
Page
IACK
Interrupt Acknowledge
13-108
Example IACK *AR5
IDLE
Page
IDLE2
LDE
Load Floating-Point Exponent
LDE
13-113
Assembly Language Instructions
Example LDE R0,R5
LDF
Page
LDFcond
Load Floating-Point Value Conditionally
13-116
Example LDFZ R3,R5
Page
LDFI
Load Floating-Point Value, Interlocked
13-118
Example LDFI *+AR2,R7
Page
LDF||LDF
Page
LDF||STF
Page
LDI
Load Integer
13-124
Example LDI *AR1(IR0),R5
Page
LDIcond
Page
LDII
Load Integer, Interlocked
13-128
Example LDII @985Fh,R3
Page
LDI||LDI
Page
LDI||STI
LDM
LDP
src,
src
LOPOWER
H1/16
Page
LSH
Page
Page
Page
Page
Page
Parallel LSH3 and STI
13-143
Assembly Language Instructions
Example 1 LSH3 R2,*++AR3(1),R0 ||STI R4,*AR5
Page
MAXSPEED
H1/16
H1
MPYF
Page
MPYF3
Multiply Floating-Point Value, 3-Operand
See Section 8.5.2,
13-148
Page
Page
Page
Page
Page
MPYF3||STF
Page
Page
Page
Page
Page
MPYI
Multiply Integer
13-160
Example MPYI R1,R5
Page
MPYI3
Multiply Integer, 3-Operand
See Section 8.5.2,
13-162
Page
Page
srcA srcD
src1 src4
Note: Cycle Count
MPYl3||ADDl3
Page
MPYI3||STI
Page
Page
srcA srcB srcD srcC
src4, src1 + src2
Note: Cycle Count
srcA srcD
src1, src4 + src2
Page
NEGB
src
dst
, src
dst
NEGF
Negate Floating-Point Value
NEGF
13-175
Assembly Language Instructions
Example NEGF *++AR3(2),R1
Page
NEGF||STF
NEGI
Page
NEGI||STI
NOP
NORM
Normalize
NORM
13-183
Assembly Language Instructions
Example NORM R1,R2
NOT
Bitwise-Logical Complement
NOT
13-185
Assembly Language Instructions
Example NOT @982Ch,R4
Page
NOT||STI
OR
Bitwise-Logical OR
OR
13-189
Assembly Language Instructions
Example OR *++AR1(IR1),R2
Page
OR3
Page
OR3||STI
POP
POPF
PUSH
PUSHF
RETIcond
Return From Interrupt Conditionally
RETIcond
13-199
Assembly Language Instructions
Example RETINZ
RETScond
Return From Subroutine Conditionally
RETScond
13-201
Assembly Language Instructions
Example RETSGE
Page
RND
ROL
Page
ROLC
Example 2 ROLC R3
ROR
RORC
Page
RPTB
Page
RPTS
SIGI
STF
STFI
Page
Page
STF||STF
STI
STII
Page
STI||STI
SUBB
Page
SUBB3
SUBC
Subtract Integer Conditionally
SUBC
13-227
Assembly Language Instructions
Example 1 SUBC @98C5h,R1
Example 2 SUBC 3000,R0 (3000 = 0BB8h)
SUBF
Subtract Floating-Point Value
SUBF
13-229
Assembly Language Instructions
Example SUBF *AR0(IR0),R5
SUBF3
Subtract Floating-Point Value, 3-Operand
SUBF3
13-231
Assembly Language Instructions
Example 1 SUBF3 *AR0(IR0),*AR1,R4
See subsection 8.5.2,
SUBF3||STF
Parallel SUBF3 and STF
SUBF3||STF
13-233
Assembly Language Instructions
Example SUBF3 R1,*AR4(IR1),R0 || STF R7,*+AR5(IR0)
See subsection 8.5.2,
SUBI
Page
SUBI3
Subtract Integer, 3-Operand
See subsection 8.5.2,
13-236
Page
SUBI3||STI
Parallel SUBI3 and STI
See subsection 8.5.2,
13-238
SUBRB
SUBRF
SUBRI
SWI
Page
TRAPcond
Trap Conditionally
13-244
Example TRAPZ 16
Page
TSTB
Test Bit Fields
13-246
Example TSTB *AR4(1),R5
Page
TSTB3
Test Bit Fields, 3-Operand
See subsection 8.5.2,
13-248
XOR
XOR3
Bitwise-Exclusive OR, 3-Operand
XOR3
13-251
Assembly Language Instructions
Example 1 XOR3 *AR3++(IR0),R7,R4
See subsection 8.5.2,
Page
XOR3||STI
Instruction Opcodes
Table A1. TMS320C3x Instruction Opcodes
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
C.1 Boot-Loader Source Code Description
Boot-Loader Source Code Description
C-3
TMS320C32 Boot Loader Source Code
Figure C1. Boot-Loader Flow Chart
C.2 Boot-Loader Source Code Listing
Page
Page
Page
Page
Page
Page
Appendix A
Appendix D
Glossary
Auxiliary-register arithmetic unit.
Arithmetic logic unit.
A
Auxiliary-register arithmetic unit.
C
See also LD0LD31
Central processing unit
D
program address generation logic.
E
F
First-in, first-out buffer.
H
I
Interrupt acknowledge signal
Least significant bit.
interrupt-trap table pointer
Interrupt service routine
M
CPU cycle
Nonmaskable interrupt
Most significant bit.
Millions of floating point operations per second
O
P
See read/write pin
Program counte
R
S
T
W
X
See also A0A23
See also D0D31
Z
Index
A
Page
B
C
D
E
F
G
H
I
algorithm 4-21 TMS320C32 2-16
L
M
N
O
P
definition D-6 memory-mapped registers
peripherals on
Page
Q
R
S
T
expansion bus I/O cycles 9-219-36 primary bus cycles 9-159-20
compared 1-5
U
V
W
X
Z
