Memory

4-13

Memory and the Instruction Cache
Figure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers
8097FFh
808068h STRB1 buscontrol
808064h STRB0 buscontrol
808060h IOSTRB buscontrol
80804Ch Serial port data receive
808048h Serial port data transmit
FSR/DR/CLKR serial port control
808046h Serial port R/X timer period
808045h Serial port R/X timer counter
808044h Serial port R/X timer control
808043h
808042h FSX/DX/CLKX serial port control
808014h
Serial port global control
808040h
Timer 1 period register
808038h
Timer 1 counter
808034h
Timer 1 global control
808030h
Timer 0 period
808028h
Timer 0 counter
808024h
Timer 0 global control
808020h
DMA 1 transfer counter
808018h
DMA 1 destination address
808016h
DMA 1 source address
808010h DMA 1 global control
DMA 0 transfer counter
808008h
DMA 0 destination address
808006h
DMA 0 source address
808004h
808000h DMA 0 global control