Toshiba SD-R6112 specifications 19/28, Timing of Host Interface Ultra DMA

6.2.4.Timing of Host Interface (Ultra DMA )

Figure 15 shows the Host Interface Ultra DMA word Timings

						tMLI
DMARQ	tUI
DMACK-
	tACK	tFS	t2CYC		tRP
STOP			tCYC	tCYC
		tENV				tACK
					tLI
DMARDY				t2CYC
		tZAD			tRFS
	tZIORDY
STROBE
		tDVS tDVH tDVS		tDVH	tDVS tDVH	tDVS tDVH
DD (15:0)						CRC
Sender
		tZAD

tZIORDY

STROBE
tDS t D H tDS	tDH tDS	tDS tDH
		tDH
DD (15:0)		CRC
Recipient

In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.

	Ultra DMA Mode 2	Min time (ns)	Max time (ns)
	Timing parameters min (ns) max (ns)
	Typical Sustained Average Cycle time	120
t2CYC
	Two cycle time (from rising edge to next rising edge of	117
	from falling edge to next falling edge of STROBE)
tCYC	Cycle time allowing	55
tDVS	Data valid Setup time	34
tDVH	Data valid Hold time	6
tUI	Unlimited Interlock time	0
tACK	Setup and Hold Time for DMACK-	20
tENV	Envelope time	20	70
tZAD	Minimum Delay time for Driver	0
tZIORDY	Minimum time for DMACK-	20
tFS	First STROBE time	0	170
tRFS	Ready-to-Final STROBE time		50
tRP	Ready-to-Pause time	100
tLI	Limited Interlock time	0	150
tMLI	Interlock with minmum	20
tDS	Data setup time (at recipient)	7
tDH	Data hold time (at recipient)	5

Figure 15 Host Interface Timing (Ultra DMA Mode 2)

19/28 SD-R6112 Rev.1.0