6.2.3.Timing of Host Interface (DMA Multi)
Figure 14 shows the Host Interface DMA multi word Timings
t0
DMARQ
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| tL | |
| tK | ||
tI | tD | ||
tJ | |||
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Read | tE | tZ | |
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| tF | |
Write |
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| tG | tH |
*1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.
| Multi word DMA | Min time (ns) | Max time (ns) |
| timing parameters min(ns) max(ns) | ||
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t0 | Cycle time | 120 |
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tC | DMACK to DMREQ delay |
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tD | 70 |
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tE | DIOR- data access |
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tF | DIOR- data hold | 5 |
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tZ | DMACK- to tristate |
| 25 |
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tG | DIOR/DIOW- data setup | 20 |
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tH | DIOW- data hold | 10 |
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tI | DMACK to | 0 |
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tJ | 5 |
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tKr | DIOR- negated pulse width | 25 |
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tKw | DIOW- negated pulse width | 25 |
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tLr | DIOR- to DMREQ delay |
| 35 |
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tLw | DIOR- to DMREQ delay |
| 35 |
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Figure 14 Host Interface Timing (Multi Word DMA Mode 2)
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