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Transcend Information TS16GCF133, TS4GCF133, TS8GCF133, TS1GCF133, CF 133X, TS32GCF133, TS2GCF133 Vcc

Models: TS1GCF133 TS32GCF133 TS16GCF133 TS2GCF133 CF 133X TS8GCF133 TS4GCF133

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TS1G~32GCF133				133X CompactFlash Card


	Signal Name	Dir.	Pin	Description
-REG		I	44	This signal is used during Memory Cycles to distinguish between Common
(PC Card Memory Mode)				Memory and Register (Attribute) Memory accesses. High for Common Memory,
Attribute Memory Select				Low for Attribute Memory.
-REG				The signal shall also be active (low) during I/O Cycles when the I/O address is on
(PC Card I/O Mode)				the Bus.

-DMACK				This is a DMA Acknowledge signal that is asserted by the host in response to
(True IDE Mode)				DMARQ to initiate DMA transfers.
				While DMA operations are not active, the card shall ignore the -DMACK signal,
				including a floating condition.
				If DMA operation is not supported by a True IDE Mode only host, this signal
				should be driven high or connected to VCC by the host.
				A host that does not support DMA mode and implements both PCMCIA and
				True-IDE modes of operation need not alter the PCMCIA mode connections
				while in True-IDE mode as long as this does not prevent proper operation all
				modes.

RESET		I	41	The CompactFlash Storage Card is Reset when the RESET pin is high with the
(PC Card Memory Mode)				following important exception:
				The host may leave the RESET pin open or keep it continually high from the
				application of power without causing a continuous Reset of the card. Under
				either of these conditions, the card shall emerge from power-up having
				completed an initial Reset.
				The CompactFlash Storage Card is also Reset when the Soft Reset bit in the
				Card Configuration Option Register is set.
RESET				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
-RESET				In the True IDE Mode, this input pin is the active low hardware reset from the
(True IDE Mode)				host.

VCC		--	13,38	+5 V, +3.3 V power.
(PC Card Memory Mode)
VCC				This signal is the same for all modes.
(PC Card I/O Mode)
VCC				This signal is the same for all modes.
(True IDE Mode)

Transcend Information Inc.

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Transcend Information TS16GCF133, TS4GCF133, TS8GCF133, TS1GCF133, CF 133X, TS32GCF133, TS2GCF133 dimensions Vcc

Contents

133X CompactFlash Card Placement FeaturesDimensions DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Signal Description DirGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Additional Requirements for CF Advanced Timing Modes Resistor is optionalSeries termination required for Ultra DMA operation 133X CompactFlash CardUltra DMA Electrical Requirements Table Typical Series Termination for Ultra DMAUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage CardsAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBADefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech Data Field Type InformationTS1G~32GCF133 0X00h Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per TrackWords 10-19 Serial Number PIO Data Transfer Cycle Timing ModeWords 7-8 Number of Sectors per Card Word 22 ECC CountMultiword DMA transfer Multiple Sector SettingTotal Sectors Addressable in LBA Mode Word 64 Advanced PIO transfer modes supportedWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security StatusValue Current PIO timing mode selected Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Word 162 Key Management Schemes SupportedValue Maximum Memory timing mode Supported Value Current Multiword DMA timing mode selectedValue Maximum Pcmcia IO timing mode Supported Idle 97h or E3hInitialize Drive Parameters 91h Idle Immediate 95h or E1hNOP 00h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported133X CompactFlash Card TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register ValuesSmart Data Structure Decription