133X CompactFlash Card | Transcend Information TS1GCF133, TS4GCF133

TS1G~32GCF133

133X CompactFlash Card

Ultra DMA Electrical Requirements

Host and Card signal capacitance limits for Ultra DMA operation

The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at 1 MHz. The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at 1 MHz.

Series termination required for Ultra DMA operation

Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table 13 describes typical values for series termination at the host and the device.

Table: Typical Series Termination for Ultra DMA

Transcend Information Inc.

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Transcend Information TS1GCF133, TS4GCF133, TS8GCF133, TS16GCF133 133X CompactFlash Card, Ultra DMA Electrical Requirements

Contents

Placement Features Dimensions133X CompactFlash Card Description Transcend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Signal Description Dir GND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Additional Requirements for CF Advanced Timing Modes Resistor is optional 133X CompactFlash Card Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Table Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing 133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage Cards Attribute Memory Function Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer Function Common Memory Transfer Function Table Common Memory Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O Decoding Contiguous I/O Mapped Addressing Table Contiguous I/O Decoding True IDE Mode Addressing Memory Mapped Addressing CF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9 Feature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h OffsetSector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h Offset TS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBA Definitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0h Flush Cache E7h Format Track 50h Identify Device Ech Data Field Type Information TS1G~32GCF133 0X00h Word 0 General Configuration Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per Track PIO Data Transfer Cycle Timing Mode Words 7-8 Number of Sectors per CardWords 10-19 Serial Number Word 22 ECC Count Multiple Sector Setting Total Sectors Addressable in LBA ModeMultiword DMA transfer Word 64 Advanced PIO transfer modes supported Words 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with Iordy Words 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and Selected Word 91 Advanced power management level value Word 160 Power Requirement DescriptionWord 89 Time required for Security erase unit completion Word 128 Security Status Value Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedValue Current PIO timing mode selected Word 162 Key Management Schemes Supported Value Current Multiword DMA timing mode selected Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported Idle 97h or E3h Initialize Drive Parameters 91h Idle Immediate 95h or E1hNOP 00h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23h TS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported 133X CompactFlash Card TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector Information Wear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register Values Smart Data Structure Decription