Signal Description, Dir | Transcend Information TS2GCF133, CF 133X

TS1G~32GCF133				133X CompactFlash Card

Signal Description

	Signal Name	Dir.	Pin	Description
A10 – A00		I	8,10,11,12,	These address lines along with the -REG signal are used to select the following:
(PC Card Memory Mode)			14,15,16,17,	The I/O port address registers within the CompactFlash Storage Card , the
			18,19,20	memory mapped port address registers within the CompactFlash Storage Card,
				a byte in the card's information structure and its configuration control and status
				registers.
A10 – A00				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
A02 - A00		I	18,19,20	In True IDE Mode, only A[02:00] are used to select the one of eight registers
(True IDE Mode)				in the Task File, the remaining address lines should be grounded by the host.

BVD1		I/O	46	This signal is asserted high, as BVD1 is not supported.
(PC Card Memory Mode)
-STSCHG				This signal is asserted low to alert the host to changes in the READY and Write
(PC Card I/O Mode)				Protect states, while the I/O interface is configured. Its use is controlled by the
Status Changed				Card Config and Status Register.
-PDIAG				In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
(True IDE Mode)				Master / Slave handshake protocol.

BVD2		I/O	45	This signal is asserted high, as BVD2 is not supported.
(PC Card Memory Mode)
-SPKR				This line is the Binary Audio output from the card. If the Card does not support
(PC Card I/O Mode)				the Binary Audio function, this line should be held negated.
-DASP				In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in
(True IDE Mode)				the Master/Slave handshake protocol.

-CD1, -CD2		O	26,25	These Card Detect pins are connected to ground on the CompactFlash Storage
(PC Card Memory Mode)				Card. They are used by the host to determine that the CompactFlash Storage
				Card is fully inserted into its socket.
-CD1, -CD2				This signal is the same for all modes.
(PC Card I/O Mode)
-CD1, -CD2				This signal is the same for all modes.
(True IDE Mode)

Transcend Information Inc.

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Image 6

Transcend Information TS2GCF133, TS4GCF133, TS8GCF133, TS1GCF133, TS16GCF133, CF 133X, TS32GCF133 Signal Description, Dir

Contents

133X CompactFlash Card Placement FeaturesDimensions Description Transcend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Signal Description Dir GND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Additional Requirements for CF Advanced Timing Modes Resistor is optional Series termination required for Ultra DMA operation 133X CompactFlash CardUltra DMA Electrical Requirements Table Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing 133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage Cards Attribute Memory Function Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer Function Common Memory Transfer Function Table Common Memory Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O Decoding Contiguous I/O Mapped Addressing Table Contiguous I/O Decoding True IDE Mode Addressing Memory Mapped Addressing CF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9 Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h Offset TS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBA Definitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0h Flush Cache E7h Format Track 50h Identify Device Ech Data Field Type Information TS1G~32GCF133 0X00h Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per Track Words 10-19 Serial Number PIO Data Transfer Cycle Timing ModeWords 7-8 Number of Sectors per Card Word 22 ECC Count Multiword DMA transfer Multiple Sector SettingTotal Sectors Addressable in LBA Mode Word 64 Advanced PIO transfer modes supported Words 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with Iordy Words 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and Selected Word 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security Status Value Current PIO timing mode selected Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Word 162 Key Management Schemes Supported Value Maximum Memory timing mode Supported Value Current Multiword DMA timing mode selectedValue Maximum Pcmcia IO timing mode Supported Idle 97h or E3h Idle Immediate 95h or E1h Initialize Drive Parameters 91hNOP 00h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23h TS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported 133X CompactFlash Card TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector Information Wear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register Values Smart Data Structure Decription