Xilinx UG018 - page 125

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 125
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
.C405JTGTDO (TDO_PPC),
.JTGC405BNDSCANTDO (),
.C405JTGTDOEN (TDO_TS_PPC),
.C405JTGEXTEST (),
.C405JTGCAPTUREDR (),
.C405JTGSHIFTDR (),
.C405JTGUPDATEDR (),
.C405JTGPGMOUT (),
...
);
JTAGPPC U_JTAG(
TDOTSPPC (TDO_TS_PPC),
TDOPPC (TDO_PPC),
TMS (TMS_PPC),
TDIPPC (TDI_PPC),
TCK (TCK_PPC)
);
endmodule;
-- Module: TWO_PPC_JTAG_SERIAL
-- Description: VHDL instantiation template for serial connection of
-- two PPC405 cores to dedicated JTAG logic
library IEEE;
use IEEE.std_logic_1164.all;
entity TWO_PPC_JTAG_SERIAL is
port (
);
end TWO_PPC_JTAG_SERIAL
architecture TWO_PPC_JTAG_SERIAL_arch of TWO_PPC_JTAG_SERIAL is
-- Component Declaration
component PPC405
port(
...
JTGC405TCK : in std_logic;
JTGC405TMS: in std_logic;
JTGC405TDI: in std_logic;
JTGC405TRSTNEG: in std_logic;
C405JTGTDO: out std_logic;
JTGC405BNDSCANTDO: in std_logic;
C405JTGTDOEN: out std_logic;
C405JTGEXTEST: out std_logic;
C405JTGCAPTUREDR: out std_logic;
C405JTGSHIFTDR: out std_logic;
C405JTGUPDATEDR: out std_logic;
C405JTGPGMOUT: out std_logic;
...
);
end component