Xilinx UG018 ISPLB Non-Pipelined Non-Cacheable Sequential Fetch

64 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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After the first miss is detected, the ICU performs a prefetch in anticipation of requiring
instructions from the next cache line (represented by the prefetch2 transaction in cycles 3
and 4). The second line read (rl2) is requested by the ICU in cycle 5 in response to the
prefetch. After the first line is read from the BIU, instructions for the second line are sent
from the BIU to the ICU fill buffer. This occurs in cycles 8 through 11. Instructions in the fill
buffer are bypassed to the instruction fetch unit to prevent a processor stall during
sequential execution (represented by the byp2 transaction in cycles 11 through 12). After all
instructions are received, they are transferred by the ICU from the fill buffer to the
instruction cache (represented by the fill2 transaction in cycles 13 through 15).
ISPLB Non-Pipelined Non-Cacheable Sequential Fetch
The timing diagram in Figure 2-10 shows two consecutive eight-word line fetches that are
not address pipelined. The example assumes the instructions are not cacheable. It also
assumes the instructions are fetched sequentially from the end of the first line through the
end of the second line. It provides an illustration of how all instructions in a line must be
transferred even though some of the instructions are discarded.
The first line read (rl1) is requested by the ICU in cycle 3 in response to a cache miss
(represented by the miss1 transaction in cycles 1 and 2). Instructions are sent from the BIU
to the ICU fill buffer in cycles 4 through 7. The target instruction is bypassed to the
instruction fetch unit in cycle 5 (byp1). Because the instructions are executing sequentially,
the target instruction is the only instruction in the line that is executed. The line is not
cacheable, so instructions are not transferred from the fill buffer to the instruction cache.
After the target instruction is bypassed, a sequential fetch from the next cache line causes a
miss in cycle 6 (miss2). The second line read (rl2) is requested by the ICU in cycle 8 in
response to the cache miss. After the first line is read from the BIU, instructions for the
second line are sent from the BIU to the ICU fill buffer. This occurs in cycles 9 through 12.
These instructions overwrite the instructions from the previous line. After loading into the
fill buffer, instructions from the second line are bypassed to the instruction fetch unit to
prevent a processor stall during sequential execution (represented by the byp2 transaction
Figure 2-9: IS PLB Pipelined Cacheable Sequential Fetch (Case 2)
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK an d CPMC40 5CLK
UG018_14_101701
PPC405 Outputs:
C405PLBICUREQUEST
C405PLBICUABUS[0:29]
adr1 adr2
fill1 fill2byp1 byp2prefetch2miss1
ICU
rl2rl1
rl2rl1
PLB/BIU Outputs:
PLBC405ICUADDRACK
PLBC405ICURDDBUS[0:63]
PLBC405ICURDWDADDR[1:3]
PLBC405ICURDDACK
rl167 rl101 rl123 rl145 rl201 rl223 rl245 rl267
d167 d101 d123 d145 d201 d223 d245 d267
02466024
PLBC405ICUBUSY