Xilinx UG018 Instruction-Side Processor Local Bus Interface

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 47

UG018 (v2.0) August 20, 2004 1-800-255-7778

Tabl e 2-5 , p ag e 4 4 shows the valid combinations of the RSTC405RESETCORE,

RSTC405RESETCHIP, and RSTC405RESETS YS sig nals and thei r ef fe ct on the D BSR[MRR]

field following reset.

This input is the JTAG test reset (TRST) signal. It can be connected to the chip-level TRST

signal. Although optional in IEEE Standard 1149.1, this signal is automatically used by the

processor block during power-on reset to properly reset all processor block logic, including

the JTAG and debug logic. When deasserted, no JTAG test reset exists.

This is a negative active signal.

Instruction-Side Processor Local Bus Interface

The instruction-side processor local bus (ISPLB) interface enables the PowerPC 405

instruction cache unit (ICU) to fetch (read) instructions from any memory device

connected to the processor local bus (PLB). The ICU cannot write to memory. This interface

has a dedicated 30-bit address bus output and a dedicated 64-bit read-data bus input . The

interface is designed to attach as a master to a 64-bit PLB, but it also supports attachment

as a master to a 32-bit PLB. The interface is capable of one transfer (6 4 or 32 bits) e very PL B

cycle.

At the chip level, the ISPLB can be combined with the data-side read-data bus (also a PLB

master) to create a shared read-data bus. This is done if a single PLB arbiter services both

PLB masters, and the PLB arbiter implementation only ret urns da ta to on e PLB ma ster at a

time.

Refer to the PowerPC Processor Reference Guide for more information on the operation of the

PowerPC 405 ICU.

Fetch requests are produced by the ICU and communicated over the PLB interface. Fetch

requests occur when an access misses the instruction cache or when the accessed memory

location is non-cacheable. A fetch request contains the following information:

xA fetch request is indicated by C405PLBICUREQUEST. See “C405PLBICUREQUEST

(Output)”.

xThe target address of the instruction to be fetched is specified by the address bus,

C405PLBICUABUS[0:29]. See “C405PLBICUABUS[0:29] (Output)”. Bits 30:31 of the

32-bit instruction-fetch address are always zero and must be tied to zero at the PLB

arbiter. The ICU always requests an aligned doubleword of data, so the byte enables

are not used.

xThe transfer size is specified as four words (quadword) or eight words (cache line)

using C405PLBICUSIZE[2:3]. See “C405PLBICUSIZE[2:3] (Output)”. The remaining

bits of the transfer size (0:1) must be tied to zero at the PLB arbiter.

xThe cacheability storage attribute is indicated by C405PLBICUCACHEABLE. See

“C405PLBICUCACHEABLE (Output)”. Cacheable transfers are always performed

with an eight-word transfer size.

xThe user-defined storage attribute is indicated by C405PLBICUU0ATTR. See

“C405PLBICUU0ATTR (Output)”.