Xilinx UG018 C405PLBICUSIZE[2:3] (Output), C405PLBICUCACHEABLE (Output)

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 53
UG018 (v2.0) August 20, 2004 1-800-255-7778
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C405PLBICUSIZE[2:3] (Output)
These signals are used to specify the line-transfer size of the instruction-fetch request. A
four-word transfer size is specified when C405PLBICUSIZE[2:3] 0b01. An eight-word
transfer size is specified when C405PLBICUSIZE[2:3] 0b10. The transfer size is valid in the
cycles during which the fetch-request signal (C405PLBICUREQUEST) is asserted. It
remains valid until the cycle following acknowledgement of the request by the PLB slave
(the PLB slave asserts PLBC405ICUADDRACK to acknowledge the request).
A four-word line transfer returns the quadword aligned on the address specified by
C405PLBICUABUS[0:27]. This quadword contains the target instruction requested by the
ICU. The quadword is returned using two doubleword or four word transfer operations,
depending on the PLB slave bus width (64-bit or 32-bit, respectively).
An eight-word line transfer returns the eight-word cache line aligned on the address
specified by C405PLBICUABUS[0:26]. This cache line contains the target instruction
requested by the ICU. The cache line is returned using four doubleword or eight word
transfer operations, depending on the PLB slave bus width (64-bit or 32-bit, respectively).
The word s return ed dur ing a li ne tran sfer can be sent from th e PLB sl ave to t he ICU i n any
order (target-word-first, sequential, other). This transfer order is specified by
PLBC405ICURDWDADDR[1:3].
C405PLBICUCACHEABLE (Output)
This signal indicates whether the requested instructions are cacheable. It reflects the value
of the cacheability storage attribute for the target address. The requested instructions are
non-cacheable when the signal is deasserted (0). They are cacheable when the signal is
asserted (1). This signal is valid during the time the fetch-request signal
(C405PLBICUREQUEST) is asserted. It remains valid until the cycle following
acknowledgement of the request by the PLB slave (the PLB slave asserts
PLBC405ICUADDRACK to acknowledge the request).
Non-cacheable instructions are transferred using a four-word or eight-word line-transfer
size. Software controls this transfer size using the non-cacheable request-size bit in the core-
configuration register (CCR0[NCRS]). This enables non-cacheable transfers to take
advantage of the PLB line-transfer protocol to minimize PLB-arbitration delays and bus
delays associated with multiple, single-word transfers. The transferred instructions are
placed in the ICU fill buffer, but not in the instruction cache. Subsequent instruction fetches
from the same non-cacheable line are read from the fill buffer instead of requiring a
separate arbitration and transfer sequence across the PLB. Instructions in the fill buffer are
fetched with the same performance as a cache hit. The non-cacheable line remains in the fill
buffer until the fill buffer is needed by another line transfer.
Cacheable instructions are always transferred using an eight-word line-transfer size. The
transferred instructions are placed in the ICU fill buffer as they are received from the PLB
slave. Subsequent instruction fetches from the same cacheable line are read from the fill
buffer during the time the line is transferred from the PLB slave. When the fill buffer is full,
its contents are transferred to the instruction cache. Software can prevent this transfer by
setting the fetch without allocate bit in the core-configuration register (CCR0[FWOA]). In
this case, the cacheable line remains in the fill buffer until the fill buffer is needed by
another line transfer. An exception is that the contents of the fill buffer are always
transferred if the line was fetched because an icbt instruction was executed.