Xilinx UG018 ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 1)

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 61
UG018 (v2.0) August 20, 2004 1-800-255-7778
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ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 1)
The timing diagram in Figure2-6 shows two consecutive eigh t-word line fetches that are
not address pipelined. The example assumes instructions are fetched sequentially from the
beginning of the first line through the end of the second line.
The first line read (rl1) is requested by the ICU in cycle 3 in response to a cache miss
(represented by the miss1 transaction in cycles 1 and 2). Instructions are sent from the BIU
to the ICU fill buffer in cycles 4 through 7. Instructions in the fill buffer are bypassed to the
instruction fetch unit to prevent a processor stall during sequential execution (represented
by the byp1 transaction in cycles 5 through 8). After all instructions are received, they are
transferred by the ICU from the fill buffer to the instruction cache. This is represented by
the fill1 transaction in cycles 9 through 11.
After the last instruction in the line is fetched, a sequential fetch from the next cache line
causes a miss in cycle 13 (miss2). The second line read (rl2) is requested by the ICU in cycle
15 in response to the cache miss. Instructions are sent from the BIU to the ICU fill buffer in
cycles 16 through 19. Instructions in the fill buffer are bypassed to the instruction fetch unit
to prevent a processor stall during sequential execution (represented by the byp2
transaction in cycles 17 through 20). After all instructions ar e rec eived, th ey ar e trans ferr ed
by the ICU from the fill buffer to the instruction cache (not shown).
Subscripts Used to identify the instruction
words returned by a transfer Read-data acknowledge ICU read-data bus
ICU forward (bypass)
(PLBC405ICURDDACK)
(PLBC405ICURDDBUS[0:63])
# Used to identify the order
doublewords are sent to the ICU Transfer order (PLBC405ICURDWDADDR[1:3])
a. The “#” symbol indicates a number.
Table 2-11: ISPLB Timing Diagram Abbreviations (Continued)
AbbreviationaDescription Where Used
Figure 2-6: ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 1)
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK an d CPMC40 5CLK
UG018_11_101701
PPC405 Outputs:
C405PLBICUREQUEST
C405PLBICUABUS[0:29] adr1 adr2
fill1byp1 byp2miss2miss1
ICU
rl2rl1
rl2rl1
PLB/BIU Outputs:
PLBC405ICUADDRACK
PLBC405ICUBUSY
PLBC405ICURDDBUS[0:63]
PLBC405ICURDWDADDR[1:3]
PLBC405ICURDDACK rl101 rl123 rl145 rl167 rl201 rl223 rl245 rl267
d101 d123 d145 d167 d201 d223 d245 d267
0246 0246