Xilinx UG018 DSPLB 3:1 Core-to-PLB Line Write

96 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide

1-800-255-7778 UG018 (v2.0) August 20, 2004

Chapter 2: Input/Output Interfaces

R

DSPLB 3:1 Core-to-PLB Line Write

The timing diagram in Figure2-27 shows a line w rite in a system with a PLB clock that

runs at one third the frequency of the PowerPC 405 clock.

The line write (wl1) is requested by the DCU in PLB cycle 2, which corresponds to

PowerPC 405 cycle 4. The BIU responds in the same cycle. The request is made in response

to a flush in PowerPC 405 cycles 1 and 2 (flush1). Data is sent from the DCU to the BIU in

PLB cycles 2 through 5 (PowerPC 405 cycles 4 through 15).

Figure 2-26: DSPLB 2:1 Core-to-PLB Line Read

Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CPMC40 5CLK

UG018_30_101701

PPC405 Outputs:

C405PLBDCUREQUEST

C405PLBDCURNW

C405PLBDCUABUS[0:31] adr1

fill1

C405PLBDCUBE[0:7]

C405PLBDCUWRDBUS[0:63]

C405PLBDCUSIZE2

DCU

rl1

PLB/BIU Outputs:

PLBC405DCUADDRACK

PLBC405DCURDDBUS[0:63]

PLBC405DCURDWDADDR[1:3]

PLBC405DCURDDACK

PLBC405DCUWRDACK

PLBC405DCUBUSY

rl1

rl101 rl123 rl145 rl167

d101 d123 d145 d167

0246

PLBCLK

Contents

Main Page Page Page Table of Contents Preface: About This Guide Chapter 1: Introduction to the PowerPC 405 Processor Chapter 2: Input/Output Interfaces Chapter 3: PowerPC 405 OCM Controller Programmers Model Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro) Timing Specification for Variable Latency (Virtex-4 DSOCM Controller Only) Application Notes and Reference Designs References Chapter 4: PowerPC 405 APU Controller Introduction FCM Instruction Processing APU Controller Configuration Interface Definition FCM Interface Timing Specification Page Preface About This Guide Guide Contents x Additional Resources x x Conventions Typographical Resource Description/URL Online Document Helvetica bold General Conventions Registers Table 1-1: General Notational Conventions Convention Definition Table 1-2: PowerPC 405 Registers Register Descriptive Name Terms Table 1-2: PowerPC 405 Registers (Continued) Register Descriptive Name Page Page Page Chapter 1 Introduction to the PowerPC 405 Processor x x x x PowerPC Architecture PowerPC Embedded-Environment Architecture x x x x Virtual Environment x Operating Environment Page PowerPC 405 Software Features x Privilege Modes Privileged Mode User Mode Address Translation Modes Real Mode Addressing Modes x x x Data Types Register Set Summary General-Purpose Registers Privileged Registers User Registers Special-Purpose Registers Machine-State Register PowerPC 405 Hardware Organization x x x x Central-Processing Unit Figure 1-2: Pow erPC 405 Organizationa CPUMMU Timers and Debug Cache Units Exception Handling Logic Memory Management Unit x x x x x x Instruction and Data Caches Timer Resources x x x x Programmable Interval Timer Fixed Interval Timer PowerPC 405 Performance Table 1-3: PowerPC 405 Cycles per Instruction Instruction Class Execution Cycles Page Chapter 2 Input/Output Interfaces Signal Naming Conventions x x x x x Table 2-1: Signal Name Prefix Definitions Prefix1 or Prefix2 Definition Location Clock and Power Management Interface x Table 2-1: Signal Name Prefix Definitions (Continued) Prefix1 or Prefix2 Definition Location CPM Interface I/O Signal Summary Figure 2-1: CP M Interface Block Symbol Table 2-2: CPM Interface I/O Signals CPM Interface I/O Signal Descriptions CPMC405CLOCK (Input) PLBCLK (Input) CPMC405CPUCLKEN (Input) CPMC405TIMERCLKEN (Input) CPMC405TIMERTICK (Input) CPMC405SYNCBYPASS (Input, Virtex-4-FX Only) CPMDCRCLK (Input, Virtex-4-FX Only) CPMFCMCLK (Input, Virtex-4-FX Only) C405CPMMSREE (Output) System Design Considerations for Clock Domains x x x x x PLB DCR Virtex-II Pro and ProX Specific Virtex-4 Specific FCM (Virtex-4-FX only) CPU Control Interface CPU Control Interface I/O Signal Summary Figure 2-2: CP U Control Interface Block Symbol Table 2-3: CPU Control Interface I/O Signals CPU Control Interface I/O Signal Descriptions TIEC405MMUEN (Input) TIEC405DETERMINISTICMULT (Input) TIEC405DISOPERANDFWD (Input) C405XXXMACHINECHECK (Output) Reset Interface x Reset Requirements x x x Reset Interface I/O Signal Summary Figure 2-3: Reset Inter face Blo ck Symbo l Table 2-6: Reset Interface I/O Signals Reset Interface I/O Signal Descriptions C405RSTCORERESETREQ (Output) C405RSTCHIPRESETREQ (Output) C405RSTSYSRESETREQ (Output) x RSTC405RESETCORE (Input) RSTC405RESETCHIP (Input) RSTC405RESETSYS (Input) JTGC405TRSTNEG (Input) Instruction-Side Processor Local Bus Interface Instruction-Side PLB Operation x Interaction with the ICU Fill Buffer Prefetch and Address Pipelining x x x x x x xNon-cacheable prefetching is enabled (CCR0[PFNC] 1). x Instruction-Side PLB I/O Signal Table Instruction-Side PLB Interface I/O Signal Descriptions Table 2-7: Instruction-Side PLB Interface Signal Summary C405PLBICUREQUEST (Output) x x x x C405PLBICUABUS[0:29] (Output) C405PLBICUSIZE[2:3] (Output) C405PLBICUCACHEABLE (Output) C405PLBICUU0ATTR (Output) C405PLBICUABORT (Output) C405PLBICUPRIORITY[0:1] (Output) Table 2-8: PLB-Request Priority Encoding Bit 0 Bit 1 Definition PLBC405ICUADDRACK (Input) x x x x PLBC405ICUSSIZE1 (Input) PLBC405ICURDDACK (Input) PLBC405ICURDDBUS[0:63] (Input) x Figure 2-5: Attachment of I SPLB Between 32-Bit Slave and 64-Bit Master PLBC405ICURDWDADDR[1:3] (Input) PLBC405ICUBUSY (Input) Table 2-10: Contents of ICU Read-Data Bus During Line Transfer PLB Slave Size Line Transfer Size Transfer OrderaICU Read-Data Bus [0:31] ICU Read-Data Bus [32:63] PLBC405ICUERR (Input) Instruction-Side PLB Interface Timing Diagrams ISPLB Timing Diagram Assumptions x Page ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 1) Table 2-11: ISPLB Timing Diagram Abbreviations (Continued) AbbreviationaDescription Where Used Figure 2-6: ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 1) ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 2) Figure 2-7: ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 2) ISPLB Pipelined Cacheable Sequential Fetch (Case 1) ISPLB Pipelined Cacheable Sequential Fetch (Case 2) Figure 2-8: IS PLB Pipelined Cacheable Sequential Fetch (Case 1) ISPLB Non-Pipelined Non-Cacheable Sequential Fetch Figure 2-9: IS PLB Pipelined Cacheable Sequential Fetch (Case 2) ISPLB Pipelined Non-Cacheable Sequential Fetch Figure 2-10: ISPLB Non-Pipelined Non-Cacheable Sequential Fetch ISPLB 2:1 Core-to-PLB Line Fetch Figure 2-11: ISPLB Pipelined Non-Cacheable Sequential Fetch PLBC405ICUBUSY ICU rl1 ISPLB 3:1 Core-to-PLB Line Fetch Figure 2-13: ISPLB 3 :1 Core-to-PLB Line Fetch ISPLB Aborted Fetch Request Data-Side Processor Local Bus Interface Figure 2-14: ISPLB Aborted Fetch Request Data-Side PLB Operation Page x Interaction with the DCU Fill Buffer Address Pipelining Unaligned Accesses Guarded Storage Data-Side PLB Interface I/O Signal Table Figure 2-15: Da ta-Side PLB Interface Block Symbol Table 2-12: Data-Side PLB Interface I/O Signal Summary Signal I/O Data-Side PLB Interface I/O Signal Descriptions C405PLBDCUREQUEST (Output) C405PLBDCURNW (Output) C405PLBDCUABUS[0:31] (Output) C405PLBDCUSIZE2 (Output) C405PLBDCUCACHEABLE (Output) C405PLBDCUWRITETHRU (Output) C405PLBDCUU0ATTR (Output) C405PLBDCUGUARDED (Output) C405PLBDCUBE[0:7] (Output) Figure 2-16: Attachment of DSPLB Between 32-Bit Slave and 64-Bit M aster C405PLBDCUPRIORITY[0:1] (Output) C405PLBDCUABORT (Output) Table 2-14: PLB-Request Priority Encoding Bit 0 Bit 1 Definition C405PLBDCUWRDBUS[0:63] (Output) x PLBC405DCUADDRACK (Input) PLBC405DCUSSIZE1 (Input) x PLBC405DCURDDACK (Input) x x x PLBC405DCURDDBUS[0:63] (Input) x PLBC405DCURDWDADDR[1:3] (Input) PLBC405DCUWRDACK (Input) Table 2-16: Contents of DCU Read-Data Bus During Eight-Word Line Transfer PLB-Slave Size Transfer Order DCU Read-Data Bus [0:31] DCU Read-Data Bus PLBC405DCUBUSY (Input) PLBC405DCUERR (Input) Data-Side PLB Interface Timing Diagrams DSPLB Timing Diagram Assumptions x DSPLB Three Consecutive Line Reads Table 2-17: DSPLB Timing Diagram Abbreviations AbbreviationaDescription Where Used DSPLB Line Read/Word Read/Line Read Figure 2-17: DSPLB Three Consecutive Line Reads DSPLB Three Consecutive Word Reads Figure 2-18: DSPLB Li ne Read/Word Read/Line Read DSPLB Three Consecutive Line Writes Figure 2-19: DS PLB Three Consecutive Word Reads DSPLB Line Write/Word Write/Line Write Figure 2-20: DSPLB Three Consecutive Line Writes DSPLB Three Consecutive Word Writes Figure 2-21: DSPLB Line Write/Wor d Write/Line Wri te DSPLB Line Write/Line Read/Word Write Figure 2-22: DSPLB Three Consecutive Word Writes DSPLB Word Write/Word Read/Word Write/Line Read Figure 2-23: DSPLB Line Write/Line Read/Word Write DSPLB Word Write/Line Read/Line Write Figure 2-24: DSPLB Word Write/Word Rea d/Word Write/L ine Read DSPLB 2:1 Core-to-PLB Line Read Figure 2-25: DS PLB Word Write/Line Read/Line Write DSPLB 3:1 Core-to-PLB Line Write Figure 2-26: DSPLB 2:1 Core-to-PLB Line Read DSPLB Aborted Data-Access Request Figure 2-27: DSPLB 3:1 Core-to-PLB Line Write Device-Control Register Interfaces Figure 2-28: DSPLB Aborted Data-Access Request x x x Internal Device Control Register (DCR) Interface Virtex-II Pro and Virtex-II ProX Note: Table 2-18: Virtex-II Pro/ProX DSOCM DCR Address Offset Device Control Register Offset Table 2-19: Virtex-II Pro/ProX ISOCM DCR Address Offset Device Control Register Offset Virtex-4-FX Table 2-20: Virtex-4-FX Internal DCR Address Offset Block Device Control Register Offset External DCR Bus Interface Figure 2-29: Dedica ted EMAC DCR Bus Interface Block Symbol x x x x Note: Figure 2-30: DCR Chain Block Diagram External DCR Bus Interface I/O Signal Summary DCR Slave Figure 2-31: DCR Bus Implementation Virtex-II Pro and Virtex-II ProX Processor Core Virtex-4-FX External DCR Bus Interface I/O Signal Descriptions C405DCRREAD/EXTDCRREAD (Output) C405DCRWRITE/EXTDCRWRITE (Output) C405DCRABUS[0:9]/EXTDCRABUS[0:9] (Output) C405DCRDBUSOUT[0:31]/EXTDCRDBUSOUT[0:31] (Output) External DCR Bus Interface Timing Diagrams DCR Interface 1:1 Clocking, Latched Acknowledge DCR Interface 1:1 Clocking, Combinatorial Acknowledge DCR Interface 2:1 Clocking, Latched Acknowledge Figure 2-34: DCR Interface 1:1 Clocking, Combinatorial Acknowledge Figure 2-35: DCR Inter face 2:1 Clocking, Latched Acknowledge The example in Figure 2-35 assumes the following: read-access or write-access request signal is deasserted. External Interrupt Controller Interface x EIC Interface I/O Signal Summary Figure 2-37: EIC Interface Block Symbol Table 2-23: EIC Interface I/O Signals EIC Interface I/O Signal Descriptions EICC405CRITINPUTIRQ (Input) Figure 2-38: JTAG Interface Block Symbol PPC405 JTAG Debug Port JTAG Interface I/O Signals JTAG Interface I/O Signal Descriptions C405JTGSHIFTDR (Output) C405JTGUPDATEDR (Output) C405JTGPGMOUT (Output) JTAG Instruction Register Figure 2-39: Defau lt Instruction Register Data Path in Virtex with Single PPC405 core Figure 2-40: Instruction Register Data Path for Series PPC405 JTAG Connect ion Table 2-25: PPC405 Instruction Opcodes Instruction Opcode Connecting PPC405 JTAG Logic Directly to Programmable I/O Figure 2-41: Incorrect Wiring of JTAG Chain with Individual PPC405 Connections Page Page Figure 2-44: Correct Wiring of JTAG Chain with Multiplexed PPC405 Connection Connecting PPC405 JTAG Logic in Series with the Dedicated Device JTAG Logic FPGA VHDL and Verilog Instantiation Templates x Page Page Page Page Page Page Debug Interface Debug Interface I/O Signal Summary Figure 2-46: Debug Interface Block Symbol Debug Interface I/O Signal Descriptions DBGC405EXTBUSHOLDACK (Input) DBGC405DEBUGHALT (Input) Table 2-26: Debug Interface I/O Signals DBGC405UNCONDDEBUGEVENT (Input) x x x C405DBGWBFULL (Output) C405DBGWBIAR[0:29] (Output) C405DBGWBCOMPLETE (Output) Trace Interface Trace Interface Signal Summary Trace Interface I/O Signal Descriptions C405TRCTRIGGEREVENTOUT (Output) C405TRCTRIGGEREVENTTYPE[0:10] (Output) Table 2-27: Trace Interface Signals C405TRCCYCLE (Output) C405TRCEVENEXECUTIONSTATUS[0:1] (Output) C405TRCODDEXECUTIONSTATUS[0:1] (Output) Table 2-28: Purpose of C405TRCTRIGGEREVENTTYPE[0:10] Signals Bit Debug Event C405TRCTRACESTATUS[0:3] (Output) Processor Version Register (PVR) Interface (Virtex-4-FX Only) PVR Interface I/O Signal Summary PVR Interface I/O Signal Descriptions Additional FPGA Specific Signals Figure 2-49: FPG A Specific Interface Block Symbol Additional FPGA I/O Signal Descriptions MCBCPUCLKEN (Input) MCBJTAGEN (Input) Page Page Chapter 3 PowerPC 405 OCM Controller Introduction x x x x x x x x Comparison of Virtex-II Pro and Virtex-4 OCM Controllers Functional Features Common Features for DSOCM and ISOCM Features for Data-Side OCM (DSOCM) Features for Instruction-Side OCM (ISOCM) x x x x x Table 3-2: DSOCM and ISOCM Features Feature Data-Side OCM Interface Instruction-Side OCM Interface OCM Controller Operation x Table 3-2: DSOCM and ISOCM Features (Continued) Feature Data-Side OCM Interface Instruction-Side Figure 3-1: OC M Controller Interfaces OCM Interface OCM DCR-Based Control Registers (Accessed Via DCR Instructions) x DSOCM Controller Load/Store Operation Non-Memory Peripherals for DSOCM Execution Re-ordering ISOCM Controller Instruction Fetch Operation x DSOCM Ports Figure 3-3: DSOCM Interface for Virtex-II Pro Figure 3-2: DSOCM Interface for Virtex-4 Data-Side On-Chip Memory (DSOCM) Controller DSOCM Input Ports Table 3-3: DSOCM Input Ports x x Note: Note: DSOCM Input Ports: Attributes x x x x Table 3-4: DSOCM Attributes Attribute Direction Description x x DSOCM Output Ports Table 3-5: DSOCM Output Ports DSOCM-to-BRAM Interfaces Note: Table 3-5: DSOCM Output Ports (Continued) Figure 3-4: DSOCM to BRAM Interface: 8-KByte Example for Virtex-II Pro PORT A PORT B Note: Figure 3-5: DSOCM to BRAM Interface: 8-KByte Example for Virtex-4 PORT A Note: PORT B ISOCM Ports Figure 3-6: DSOC M to Memory-Mapped Slave Peripheral (Virtex-4 Extended Feature) Figure 3-7: ISOC M Interface for Virtex-II Pro ISOCM Input Ports Figure 3-8: ISOC M Interface for Virtex-4 Table 3-6: ISOCM Input Ports x x ISOCM Input Ports, Attributes ISOCM Output Ports Table 3-8: ISOCM Output Ports Table 3-8: ISOCM Output Ports (Continued) Figure 3-9: IS OCM to BRAM Interface: 8 KByte Example in Virtex-II Pro PORT B PORT A Note: Figure 3-10: ISOCM to BRAM Interface: 8 KByte Example in Virtex-4 Programmers Model DCR Registers DSARC/ ISARC Registers PORT B PORT A DSCNTL Registers Table 3-9: DSCNTL Register for Virtex-II Pro ISCNTL Registers Table 3-10: DSCNTL Register for Virtex-4 Table 3-11: ISCNTL Register for Virtex-II Pro Features Introduced in Virtex-4 and Comparison with Virtex-II Pro Table 3-12: ISCNTL Register for Virtex-4 Figure 3-11: DSOCM DCR Registers for Virtex-II Pro Figure 3-12: DSOCM DC R Registers for Virtex-4 Figure 3-13: ISOCM DCR Register s for Virtex-II Pro Figure 3-14: ISOCM DCR Register s for Virtex-4 DCR Write Access Figure 3-15: ISOCM : ISINIT and ISFILL Descriptions (Write Access) for Virtex-II Pro and Virtex-4 DCR Read Access x Figure 3-16: ISOCM: ISINIT and ISFILL Descriptions (Read Access) for Virtex II-Pro Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro) Note: Figure 3-17: IS OCM: ISINIT and ISFILL Descriptions (Read Access), for Virtex-4 Single-Cycle Mode Multi-Cycle Mode ISOCM Instruction Fetching Figure 3-18: Instruction Fetch Timing Writing to ISBRAM Figure 3-19: Multi-Cycle Mode (2:1) Instruction Fetch Timing Figure 3-20: S ingle Cycle Mode (1:1) ISOCM Write Timing DSOCM Data Load, Fixed Latency Figure 3-21: Multi C ycle Mode (2:1) ISOCM Write Timing Figure 3-22: Single Cycle Mode (1:1) Data Load Timing Figure 3-23: Multi Cycle Mode (2:1) Data Load Timing DSOCM Store, Fixed Latency Figure 3-24: Single Cycle Mode (1:1) Data Store Timing Timing Specification for Variable Latency (Virtex-4 DSOCM Controller Only) Figure 3-25: Multi Cycle Mode (2:1) Data Store Timing DSOCM Data Load, Variable Latency Note: Figure 3-26: Single Cycle Mode (1:1) DSOCM Read Variable Latency for Virtex-4 Note: DSOCM Data Store, Variable Latency Figure 3-27: Multi Cycle Mode (2:1) DSOCM Read Variable Latency Virtex-4 Note: Figure 3-28: S ingle Cycle Mode (1:1) DSOCM Write Variable Latency Virtex-4 Figure 3-29: Multi C ycle Mode (1:2) DSOCM Write Variable Latency Virtex-4 Application Notes and Reference Designs References Page Chapter 4 PowerPC 405 APU Controller Introduction FCM Instruction Processing Figure 4-1: Pipeline Flow Diagram Enabling the APU Controller Instruction Classes Autonomous Instructions Non-autonomous Instructions Table 4-1: APU Controller-Related MSR Bits Bit(s) in MSR Description Instruction Format Figure 4-2: FCM Instruction Format Table 4-2: APU Op-codes Primary Op-code Extended Op-code Description Instruction Decoding APU Controller Pre-Defined Instruction Decoding Floating Point Instructions Table 4-2: APU Op-codes (Continued) Primary Op-code Extended Op-code Description Note: FCM Load/Store Instructions Note: APU Controller User-Defined Instruction Decoding FCM Pre-Defined Instruction Decoding x Integer Divide Instructions Table 4-3: Load/Store Extended Op-code Field Bit position Description FCM User-Defined Instruction Decoding FCM Exceptions FCM Instruction Flushing x x x APU Controller Configuration General Configuration Register Table 4-4: APU Controller Configuration Register Bit Description UDI Configuration Registers Table 4-4: APU Controller Configuration Register Bit Description (Continued) Table 4-5: UDI Configuration Register Bit Description DCR Access to the Configuration Registers Interface Definition Table 4-5: UDI Configuration Register Bit Description (Continued) APU Controller Input Signals Table 4-6: FCM Interface Input Signals Signal Function Page APU Controller Output Signals Table 4-7: FCM Interface Output Signals Signal Function x x APU Controller Attributes Table 4-8: APU Controller Attributes Attribute Signal Function Page FCM Interface Timing Specification Autonomous Transactions Figure 4-3: APU Controller Decoded Autonomous Transaction Example and operands can be valid on the same FCM clock cycle, or they can be many cycles apart. Note: Figure 4-4: FCM Decoded Autonomous Transaction Example Blocking Transactions Figure 4-5: FCM Decoded Blocking Transaction Example Note: Non-Blocking Transactions Figure 4-6: A PU Controller Decoded Non-Blocking Transaction Example Note: FCM Load Instruction Figure 4-7: APU Controller Decoded Load Instruction Example Note: in Figure 4-7. Figure 4-8: APU Controller Decoded a Double Word Load Instruction with LoadWait Example FCM Store Instruction FCM Exception Figure 4-10: APU Controller Decoded Store Instruction with StoreWBOK=1 Figure 4-11: FCM Exception Note: instruction. FCM Decoding Using Decode Busy Signal Figure 4-12: FCM Decode Asserting DecodeBusy Figure 4-13: FCM Deas ser ti ng DecodeBu s y Appendix A RISCWatch and RISCTrace Interfaces Figure A-1: JTAG-Connector Physical Layout RISCWatch Interface Appendix A: RISCWatch and RISCTrace Interfaces Table A-1: JTAG Connector Signals for RISCWatch Pin RISCWatch Description I/O Signal Name RISCTrace Interface Appendix A: RISCWatch and RISCTrace Interfaces Table A-3: Trace Connector Signals for RISCTrace Pin RISCTrace Description I/O Signal Name Page Page Appendix B Signal Summary Interface Signals Table B-1: PowerPC 405 Interface Signals in A lphabetical Order Page Page Page Page Page Page Page Page Page Appendix C Processor Block Timing Model Figure C-1: PowerP C 405 Processor Block (Simplified) IBM PPC405 Processor Block Timing Parameter Tables and Diagram Table C-2: Parameters Relative to the Core Clock (CPMC405CLOCK) Page Table C-3: Parameters Relative to the DCR Bus Clock (CPMDCRCLK, Virtex-4 Only) Table C-4: Parameters Relative to the FCM Clock (CPMFCMCLK, Virtex-4 Only) Table C-4: Parameters Relative to the FCM Clock (CPMFCMCLK, Virtex-4 Only) (Continued) Table C-5: Parameters Relative to the PLB Clock (PLBCLK) Table C-5: Parameters Relative to the PLB Clock (PLBCLK) (Continued) Table C-6: Parameters Relative to the JTAG Clock (JTAGC405TCK) Table C-7: Parameters Relative to the ISOCM Clock (BRAMISOCMCLK) Table C-7: Parameters Relative to the ISOCM Clock (BRAMISOCMCLK) (Continued) Table C-8: Parameters Relative to the DSOCM Clock (BRAMDSOCMCLK) Figure C-2: Processor Block Timing Relative to Clock Edge Index A B C D G I J L M R S T U V