Intel 537EX manual 16C550A Uart Fifo Operation, Fifo Interrupt Mode Operation, 102

Page 102

Parallel Host Interface 16C450/16C550A UART

9.316C550A UART FIFO Operation

The modem 16C550A UART FIFO works in both interrupt and polled operation. A description of each type of operation is provided below.

9.3.1FIFO Interrupt Mode Operation

Both the modem receiver and transmitter UART FIFOs can be set up for interrupt mode operation. The RCVR FIFO trigger level and character time-out interrupts have the same priority as the current received data available interrupt. The XMIT FIFO empty interrupt has the same priority as the Transmitter Holding register empty interrupt. Information pertaining to using the receiver and transmitter FIFO interrupts is provided below.

1.When both the receiver FIFO and the receiver interrupts are enabled (FCR0 = 1, IER0 = 1), the UART initiates RCVR interrupts under the following conditions:

a.The receive data available interrupt (IIR = 04) is issued to the DTE when the FIFO has reached its programmed trigger level; the interrupt clears as soon as the FIFO drops below the programmed trigger level

b.The data ready bit, DR (LSR0), is set as soon as a character is transferred from the Internal Shift register to the RCVR FIFO. DR is reset when the FIFO is empty.

2.When the RCVR FIFO and receiver interrupts are enabled, the UART initiates a RCVR FIFO time-out interrupt under the following conditions:

a.A RCVR FIFO time-out occurs when:

At least one character is in the FIFO.

The most recent serial character received was longer than four continuous character times ago.

The most recent DTE read of the FIFO was longer than four continuous character times ago.

b.When a time-out interrupt has occurred, then it is cleared and the timer is reset when the DTE reads one character from the RCVR FIFO.

c.The time-out timer is reset after a new character is received or after the DTE reads the

RCVR FIFO.

3.When the transmitter FIFO and the transmitter interrupt are enabled (FCR0 = 1, IER1 = 1), the UART initiates XMIT interrupts under the following conditions:

a.The Transmitter Holding register interrupt (IIR = 02) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to or the IIR is read. During servicing, the 1–16 character interrupt can be written to the XMIT FIFO.

9.3.2FIFO Polled Mode Operation

Both the modem receiver and transmitter UART FIFOs can be set up for polled mode operation. The UART FIFO is set for polled mode when FIFOE (FCR0) = 1 and the respective interrupt enable bit (IER) = 0.

In polling mode, the DTE checks the LSR for receiver and/or transmitter status. The LSR register provides the following information:

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536EX Chipset Developer’s Manual

Intel Confidential

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Contents 537EX Chipset Developer’s ManualIntel Confidential Contents Figures Tables Revision History Date Revision Description001 Initial release Introduction Controllerless Modem Driver OverviewWindows 95 and Windows Unimodem V.90/V.92 and V.34 Data ModesTapi Intelsdb.VXDModem Connection Overview DCE-to-DCE Data Rates for Each Mode AT Commands OverviewDTE-to-DCE Data Rates for Each Mode DCE-to-ISP Data Rates for V.90 ModeDTE-Modem Data Rate Response Codes Sending CommandsDelayed Call Numeric TextDial Modifier Command FunctionAT Escape Sequences Dialing digitsData Mode Command Summary Command Function Default Range Reported By &VnIntel Confidential Intel Confidential Intel Confidential +ESR +EB+ESA +ETBM44/V.42/V.42 bis MNP Command Summary Processes flow control characters and passes to local Fax Identity Command Summary Fax Class 1 Command SummaryIS-101 Voice Command Summary Voice DTE→DCE Character PairsResponse Hex Code Function DEL Voice DTE →DCE Character PairsVoice DTE←DCE Character Pairs ESCRegister Summary Register Function Default Range Units Reported by &VnDial Modifiers AsciiRegister Function Default Range Units Using AT Commands to Access the S-Registers Sn?, Sn=x, ? Modem Responses and Command Echo En, Vn, Xn, Wn, QnModem Setup Host Modem Response Command Disable Enable Data Reporting Wn MappingDTE Resets and then configures the modem to Nvram user profile AT Commands Product Information Establishing a Modem Connection A, D, DS = n, S0Product Identification Information Online Command Mode Escape Codes, On Hanging Up Hn, S10, Zn, &D2Modem-to-Modem Connection Data Rates Intel Confidential Modem-on-Hold Incoming Voice Call in Data Mode Modem-on-Hold Initiating a Voice Call in Data Mode Intel Confidential Supported Modulation Types Carrier DescriptionDiagnostic Testing S18, &Tn Local Analog Loopback AT&T1Local Analog Loopback With Self-Test AT&T8 Local Modem or Test ModemAT Escape Sequences Time-Independent Escape SequenceLicensing Requirements for Hayes Escape Sequence Example Data Mode Command Descriptions Command Default DescriptionHayes* Escape Sequence Echo disabled Previously stored in the Nvram with the AT&Zn=x commandHost in either online or off-line command mode Echo enabledATI2 DTESn=x Numeric or verbose form CommandModem dials a telephone number touch tone dialing Numeric formResets the modem and recalls user profile DisconnectingSubsequent commands to be ignored DCD or Rlsd signalStored Profile AT&V0Active Profile Telephone NumbersSelect profile S-register configurations into the Nvram user profile ‘n’Command to see the stored telephone number = 0-9 a B C D # * T P R W @Command Default Indication Definition+EB Secondary channel operation, and vice versa CRC generation and checking disabledNrzi encoding and decoding disabled 12/V.34+ESR +ETBM+IFC +GMR+GSN +ILRR=m= carrier,carrier,…carrier +MS command description+MA? will display a list of enabled alternative modulations If +MS = ,0,, no alternative modulations will be availableBELL212 Carrier DescriptionBELL103 +MS=m See ‘m’Value Description +PHSW=+PMHF +PMHREnable Short Phase Conjunction with the +PSS commandEnable Short Phase 1 and Short Phase Disable short Phase 1 and Short PhaseMode Features Operating ModesResulting +ES Connection Types 44/V.42/V.42 bis and MNP Data Modem Command Descriptions+ES Settings Answer Modem +ES=1, 0 +ES=4, 4 +ES=3, 0 +ES=3, 2\Bn \Kn +DS=m +DR=mDirection Max string3768 +EFCS=m+ER=m Display messages when +ER =Decimal value and the format is as follows +ER LapmNon-error control operation Setting is ignored if origrqst=6Control during non-error control operation +ES=mFax Identity Command Descriptions Fax Identity CommandsFax Class 1 Commands +FMFR?/+FMIMod Selection Table Value Modulation Speed bps30 Hdlc Frame Format Class 1 DTE-Generated Hdlc Frame Information AT+FTH=modFax Mode Command Descriptions +FCLASS?+FCLASS +FRH=m +FRS=m+FTH=m IS-101 Voice Mode AT Commands Voice Mode Command Descriptions Dtmf Detection ReportingRelay Control +FLO=m Enable report Function +VDR=m See ‘m’Event Description Defaults = ‘C’, BB860980, BFE63883, BB863EE0Caller ID report Command Reserved Distinctive ringing All +VEM=m See ‘m’EIGHT-DIGIT HEX Code B B 8 6 3 E E EX Value BIT Value EventHEX Digit Location Local telephone, or speaker 128 Nominal transmit level+VIP Preassigned Voice I/O Labels Label+VLS=m Voice I/O Primitive Codes Relay/Playback ControlPrimitive Code Description +VRX +VSD=m See ‘m’+VSM=m +VSM=? command to obtain supported sampling rates141 AD3 3-bit Adaptive differential pulse code modulation Range 4800, 7200, 8000, and 11025 samples/secondHard Disk CmlSerial Compression100 Factory default is ‘0’100 Default value 1 second Range 5-255 units of 0.01 secondsSpecified by +VTD=m Dual tones may be sent using the following format+VTS=m None This sends a 500 ms period of silenceCommand Default Description Register Command Descriptions S10 Range Seconds Default 0 seconds Escape sequencesS16 S25 S21S22 118 S30Sleep mode is disabled by setting S33 to ‘0’ Modem exits sleep mode whenever the host reads or writes toModem or when a ring signal is detected Inactive state whenCaller ID Tags for Formatted Reporting Tag DescriptionRing Uart Emulation in the Controllerless Modem Uart Emulation in Intelsdb.VxDUart THRRBR Parallel Host Interface Uart Register Bit Assignments Uart Register Definitions Scratch Register SCRModem Status Register MSR Line Status Register LSR Bit Framing errorOE Overrun Error-Not supported StackModem Control Register MCR IER Interrupt Enable registerProcedure is as follows Line Control Register LCRFifo Control Register FCR BitInterrupt Identity Register IIR Interrupt Control FunctionsID1 ID0 Transmitter Holding Register THR Interrupt Enable Register IERID bit 2 for Fifo mode Dlab =Programmable Data Rates Receiver Buffer Register RBRDivisor Latch Registers DLM and DLL Data Rate Divisor Number Divisor Latch Hex16C550A Uart Fifo Operation Fifo Interrupt Mode OperationFifo Polled Mode Operation 102536EX Chipset Developer’s Manual 103

537EX specifications

The Intel 537EX is a powerful and innovative embedded processor designed for a range of applications, particularly in the fields of industrial automation, telecommunications, and transport management systems. This processor is a member of Intel's embedded product line, tailored specifically to meet the demands of systems that require high reliability and long lifecycle support.

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