Intel IXP12xx manual Version 1.0, 4/10/02

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Version 1.0, 4/10/02

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The IXP12xx ATM OC12/Ethernet IP Router Example Design may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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*Other brands and names are the property of their respective owners. Copyright © Intel Corporation 2002

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Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Alternate Dram Timing OverviewMeasurement Environment Single Cell PDU Workload KEY Workloads & Approaches to Testing the Example DesignProtocol Performance of IP over ATM vs. Ethernet Frame and PDU Length versus IP Packet Length Cycle Budgets to support Line Rates Multiple Cells/PDU WorkloadCycle and Instruction Budgets Cycles/cellUsec/frame = 1559 cycles/frame Cells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7ESimulation Measurement Procedure and Results Simulated 29-byte packet performance1Hardware Measurement Results Hardware Measurement Procedure and ResultsSimulated 40-byte and 1500-byte packet performance2 Single-cell/PDU Performance using 133MHZ Dram Hardware 29-byte packet performance9.5 Hardware 40-byte packet performance138 142 144 88,300517 Hardware 1500-byte packet performance518 Ethernet Queue to Core Throughput Queue to Core Measurement TechniqueATM Queue to Core Throughput Resource Utilization and Headroom Analysis Microengine Register and Microstore HeadroomScratchpad RAM Capacity Sram CapacitySdram Capacity Sram and Sdram BandwidthAppendix Buffer Allocation in Dram