Intel IXP12xx Simulated 40-byte and 1500-byte packet performance2, Hardware Measurement Results

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Version 1.0, 4/10/02

Both the OC-12 and 4xOC-3 configurations experience an ATM overflow after 1M cycles. This indicates that under this system workload, the receiver is not keeping up with the wire, but has dropped a cell in the first 6,000 cells.

Simulated 40-byte and 1500-byte packet performance2

The OC-12 and 4xOC-3 configurations perform at ATM wire-rate under full-duplex, full- bandwidth 40-byte and 1500-byte packet loads.

HARDWARE MEASUREMENT PROCEDURE AND RESULTS

While simulation provides a high degree of visibility into the design, there are several important benefits to measuring on hardware:

1.The ability to do experiments on large numbers of packets. The simulator receives about 10 cells/second, whereas the hardware can receive OC-12 data at 1.4M cells/second. Thus events that take a long time to occur on the simulator occur almost immediately on the hardware.

2.Unplanned error conditions occur regularly on the hardware due to hot plugging cables, optical and electrical noise, mis-configured lab equipment or random error injection via lab equipment, etc – and the design must handle them correctly.

3.The Transactor simulator does not model DRAM refresh overhead, and so configurations that are sensitive to DRAM bandwidth will notice a small performance hit on the hardware versus simulation.

To measure the design in the lab, an ADTECH AX/4000 is attached to the ATM ports, and a Smartbits 600 is attached to the 8 Ethernet ports.

Both pieces of equipment simultaneously generate traffic (at line-rate), and also observe the data that is being transmitted through the system from the other end of the design. Example AX/4000 sequence files are included in the project under atm_ether\tools\AX4000.

After the experiment, the Octal MAC and the IXF6012 “Volga” PHY counters are checked for evidence of underflows or overflows. Specifically, for the PHY, idle cells sent or received are searched for, as these would indicate that the ATM links were not fully utilized.

The Counters_print() command at the VxWorks* command line also displays if the microcode discarded any packets, and why.

Hardware Measurement Results

Only the OC-12 configuration results are detailed here, as no WAN daughter-card was available with 4xOC-3 ports.

ATM Transmit Rate is expressed as a percentage of OC-12 wire rate, as received and reported by the AX/4000. IXF6012 Transmit Idle cells are reported by “_VolgaGetChanCounters” to report

2Simulations for 29-byte, 40-byte, and 1500-byte packet loads were run using 133 MHz memory (-75).

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Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Overview Measurement EnvironmentAlternate Dram Timing KEY Workloads & Approaches to Testing the Example Design Protocol Performance of IP over ATM vs. EthernetSingle Cell PDU Workload Frame and PDU Length versus IP Packet Length Cycle and Instruction Budgets Multiple Cells/PDU WorkloadCycle Budgets to support Line Rates Cycles/cellCells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7E Usec/frame = 1559 cycles/frameSimulated 29-byte packet performance1 Simulation Measurement Procedure and ResultsHardware Measurement Procedure and Results Simulated 40-byte and 1500-byte packet performance2Hardware Measurement Results Hardware 29-byte packet performance Single-cell/PDU Performance using 133MHZ Dram138 142 144 Hardware 40-byte packet performance9.5 88,300Hardware 1500-byte packet performance 518517 Queue to Core Measurement Technique ATM Queue to Core ThroughputEthernet Queue to Core Throughput Microengine Register and Microstore Headroom Resource Utilization and Headroom AnalysisSram Capacity Scratchpad RAM CapacitySram and Sdram Bandwidth Sdram CapacityBuffer Allocation in Dram Appendix
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