Version 1.0, 4/10/02
APPENDIX
Buffer Allocation in DRAM
The microengines in this example design uses two DRAM command queues. The ordered queue is used by all sdram_crc[] commands to transfer packet data between DRAM and the receive and transmit FIFOs. The priority queue is used for all other microengine DRAM accesses, including access to IP lookup table entries, and modifications to packet headers.
While the instruction set mandates that the sdram_crc[] commands use the ordered queue, the design has the flexibility to use different queues for the other DRAM accesses. system_config.h defines DRAM_QUEUE to either "ordered", "optimize_mem", or "priority", for this purpose. The choice of the priority queue as the default was made by comparing the alternatives for the
As described in the IXP1200 Hardware Reference Manual, the IXP12xx performs "Active Memory Optimization" to eliminate latencies when it accesses different DRAM banks. This is true even if the chip uses the ordered and priority queues as in this design. Thus there is a performance benefit if the system's DRAM accesses frequently alternate between DRAM banks.
To take advantage of this optimization, the DRAM data buffer pool is positioned to equally span multiple DRAM banks. Further, the descriptor freelist describing this pool is initialized such that subsequent buffer allocations refer to buffers from alternate DRAM banks.
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