Intel IXP12xx manual Multiple Cells/PDU Workload, Cycle and Instruction Budgets, Cycles/cell

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Version 1.0, 4/10/02

As shown graphically in Figure 3, 622Mbps of single-cell-PDU input requires 622*(84/55) = 949 Mbps of Ethernet output.

This example design supplies 800Mbps of Ethernet bandwidth (IXP1240 configurations), so under a single cell/PDU workload the design can be expected to transmit Ethernet at line rate, and to discard the excess ATM input. In the reverse direction, if Ethernet data is received at wire rate (even with all 8 ports running at wire-rate), ATM transmit will not be saturated under a single cell/PDU workload.

Multiple Cells/PDU Workload

Following Figure 2 from left to right, it is clear that once a PDU size overflows from one cell into two, Ethernet becomes more efficient in terms of Mbps.

When the packet completely fills two or three cells, ATM is again more efficient, but not by much. For example, two full cells require 622(118/110) = 666 Mbps; and three full cells require 622/(166/159) = 625 Mbps of Ethernet bandwidth for 622Mbps of ATM bandwidth. These numbers are well below the 800Mbps of Ethernet bandwidth available in the example configuration.

Thus for multi-cell/PDU workloads, this design has more Ethernet bandwidth available than ATM bandwidth, and excess Ethernet input will be discarded. In the reverse direction, Ethernet transmit bandwidth will not be exceeded even if all ATM ports receive data at wire-rate (Figure 3).

While this design supports any IP packet size between 20 and 1500 bytes, 40 byte packets are expected to be the most common. 40-byte packets corresponds to a 20-byte IP header plus a 20- byte TCP header, with no payload. 40-byte IP packets form AAL5 PDUs that consume 2 ATM cells.

The largest PDU supported by the design contains a 1500-byte packet. This packet is carried by a 1518-byte Ethernet frame or by a 32-cell AAL5 PDU.

CYCLE AND INSTRUCTION BUDGETS

Cycle Budgets to support Line Rates

OC-12 line rate is 622Mbps, but SONET overhead reduces it to 599Mbps available to ATM cells. 53 bytes/cell * 8 bits/byte / 599 Mb/sec = 708 ns/cell. So 232MHz * 708 ns/cell = 164

cycles/cell.

OC-3 line rate is 155Mbps, but SONET overhead reduces it to 149Mbps available to ATM cells. 53 bytes/cell * 8 bits/byte / 149 Mb/sec = 2.85 us/cell. So 232MHz * 2.85 us/cell = 660 cycles/cell.

Ethernet has a variable sized frame, and thus a variable per-frame cycle budget. The worst-case is minimum-sized 64-byte frames, thus they are the focus for per-frame calculations here. A 64- byte frame actually occupies 84 bytes on the wire. {(12 byte Inter Packet Gap) + (8 byte preamble) + (46 byte IP packet) + (14 byte Ethernet Header) + (4 byte Ethernet FCS) = 84

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Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Overview Measurement EnvironmentAlternate Dram Timing KEY Workloads & Approaches to Testing the Example Design Protocol Performance of IP over ATM vs. EthernetSingle Cell PDU Workload Frame and PDU Length versus IP Packet Length Cycle Budgets to support Line Rates Multiple Cells/PDU WorkloadCycle and Instruction Budgets Cycles/cellUsec/frame = 1559 cycles/frame Cells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7ESimulation Measurement Procedure and Results Simulated 29-byte packet performance1Hardware Measurement Procedure and Results Simulated 40-byte and 1500-byte packet performance2Hardware Measurement Results Single-cell/PDU Performance using 133MHZ Dram Hardware 29-byte packet performance9.5 Hardware 40-byte packet performance138 142 144 88,300Hardware 1500-byte packet performance 518517 Queue to Core Measurement Technique ATM Queue to Core ThroughputEthernet Queue to Core Throughput Resource Utilization and Headroom Analysis Microengine Register and Microstore HeadroomScratchpad RAM Capacity Sram CapacitySdram Capacity Sram and Sdram BandwidthAppendix Buffer Allocation in Dram