Intel IXP12xx manual Hardware 1500-byte packet performance, 518, 517

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Version 1.0, 4/10/02

Ethernet

ATM

IXF6012

ATM

IXF6012

Input

Transmit

Transmit

Receive

Overflows

Ports

Rate [%]

Idle

Ports

 

8

100

0

1

0

Figure 8Two-cell/PDU Performance on 143MHZ DRAM

Ethernet

Transmit

KFrame/s

88,300

Ethernet

Transmit

[MB/s]

5.6

Using 143 MHz DRAM, the 40-byte (2-cell/PDU) workload performed perfectly, even with 8 Ethernet ports over-subscribing the ATM Transmitter (Figure 8). “_VolgaGetChanCounters” recorded zero ATM Transmit Idle cells and zero ATM Receive overflows.

This illustrates the sensitivity of the design to DRAM speed grade selection.

Hardware 1500-byte packet performance

Ethernet

ATM

IXF6012

ATM

IXF6012

Input

Transmit

Transmit

Receive

Overflows

Ports

Rate [%]

Idle

Ports

 

8

100

2

1

500

7

100

0

1

200

6

100

0

1

0

5

92

N/A

1

0

Figure 932-cell/PDU Performance on 133MHz DRAM

Ethernet

Transmit

KFrame/s

5,450

5,518

5,518

5,518

Ethernet

Transmit

[MB/s]

8.33

8.37

8.37

8.37

Results for 1500-byte packets (32-cells/PDU) were similar to the 2-cell case. The design worked flawlessly with six input Ethernet ports. Five ports was not enough to drive ATM to saturation, and the design degraded slightly as it was over-subscribed by adding the 7th and then 8th Ethernet input port (Figure 9).

Ethernet

ATM

IXF6012

ATM

IXF6012

Input

Transmit

Transmit

Receive

Overflows

Ports

Rate [%]

Idle

Ports

 

8

100

0

1

0

Figure 1032-cell/PDU Performance on 143 MHz DRAM

Ethernet

Transmit

KFrame/s

5,517

Ethernet

Transmit

[MB/s]

8.37

Analogous to the 2-cell/PDU case, the 32-cell/PDU case performed perfectly using 143 MHz DRAM, even in the face of over-subscription with 8 Ethernet input ports and “_VolgaGetChanCounters” running on the core (Figure 10).

StrongARM CORE PERFORMANCE

This example design sends exception cells, PDUs and frames to the StrongARM core. It uses up to 4 message queues for this purpose – one for each of the microengines that can send data to the core. The core is alerted by an interrupt when data is put into the core message queues.

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Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Overview Measurement EnvironmentAlternate Dram Timing KEY Workloads & Approaches to Testing the Example Design Protocol Performance of IP over ATM vs. EthernetSingle Cell PDU Workload Frame and PDU Length versus IP Packet Length Multiple Cells/PDU Workload Cycle and Instruction BudgetsCycle Budgets to support Line Rates Cycles/cellUsec/frame = 1559 cycles/frame Cells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7ESimulation Measurement Procedure and Results Simulated 29-byte packet performance1Hardware Measurement Procedure and Results Simulated 40-byte and 1500-byte packet performance2Hardware Measurement Results Single-cell/PDU Performance using 133MHZ Dram Hardware 29-byte packet performanceHardware 40-byte packet performance 138 142 1449.5 88,300Hardware 1500-byte packet performance 518517 Queue to Core Measurement Technique ATM Queue to Core ThroughputEthernet Queue to Core Throughput Resource Utilization and Headroom Analysis Microengine Register and Microstore HeadroomScratchpad RAM Capacity Sram CapacitySdram Capacity Sram and Sdram BandwidthAppendix Buffer Allocation in Dram