Intel IXP12xx KEY Workloads & Approaches to Testing the Example Design, Single Cell PDU Workload

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Version 1.0, 4/10/02

KEY WORKLOADS & APPROACHES TO TESTING THE EXAMPLE DESIGN

Protocol Performance of IP over ATM vs. Ethernet

Figure 1 details the protocol processing required to carry an IP packet over ATM and Ethernet. .

Figure 1 – Protocol Processing

Figures 2 and 3 show that as the size of the IP packet varies so do the efficiencies of ATM and Ethernet. This section details those efficiencies and the resulting performance implications

Single Cell PDU Workload

Single-cell PDUs result from IP packets of size 20 to 32 bytes – for example UDP packets with up to 4 payload bytes (8 bytes of LLC/SNAP plus 8 bytes of AAL5 trailer are included with the IP packet in the 48-byte cell payload). Adding a 4-byte ATM cell header plus 1-byte HEC results in a 53-byte cell. SONET overhead transparently adds about another 2 bytes/cell to the wire-time such that its total cost is 55-bytes in terms of a 155 or 622 Mbps ATM link.

When the same packet is carried over Ethernet, it expands to consume a minimum-sized 64-byte frame. Ethernet then adds at least 960ns of inter-packet gap (12-bytes), plus a preamble (8- bytes). The total packet cost is 84-bytes on a 100Mbps Ethernet link.

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Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Measurement Environment OverviewAlternate Dram Timing Protocol Performance of IP over ATM vs. Ethernet KEY Workloads & Approaches to Testing the Example DesignSingle Cell PDU Workload Frame and PDU Length versus IP Packet Length Multiple Cells/PDU Workload Cycle and Instruction BudgetsCycle Budgets to support Line Rates Cycles/cellUsec/frame = 1559 cycles/frame Cells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7ESimulation Measurement Procedure and Results Simulated 29-byte packet performance1Simulated 40-byte and 1500-byte packet performance2 Hardware Measurement Procedure and ResultsHardware Measurement Results Single-cell/PDU Performance using 133MHZ Dram Hardware 29-byte packet performanceHardware 40-byte packet performance 138 142 1449.5 88,300518 Hardware 1500-byte packet performance517 ATM Queue to Core Throughput Queue to Core Measurement TechniqueEthernet Queue to Core Throughput Resource Utilization and Headroom Analysis Microengine Register and Microstore HeadroomScratchpad RAM Capacity Sram CapacitySdram Capacity Sram and Sdram BandwidthAppendix Buffer Allocation in Dram